FDRSE.v
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// $Header: /root/leakn64/depot/rf/hw/flif/xilinx/FDRSE.v,v 1.1 2003/08/20 23:46:46 berndt Exp $
/*
FUNCTION : D-FLIP-FLOP with sync reset, sync set and clock enable
*/
`timescale 100 ps / 10 ps
module FDRSE (Q, C, CE, D, R, S);
parameter INIT = 1'b0;
output Q;
reg q_out;
input C, CE, D, R, S;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR)
if (GSR)
assign q_out = INIT;
else
deassign q_out;
always @(posedge C)
if (R)
q_out <= 0;
else if (S)
q_out <= 1;
else if (CE)
q_out <= D;
specify
if (R)
(posedge C => (Q +: 1'b0)) = (1, 1);
if (!R && S)
(posedge C => (Q +: 1'b1)) = (1, 1);
if (!R && !S && CE)
(posedge C => (Q +: D)) = (1, 1);
endspecify
endmodule