RAM32X1D.v
1.62 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
// $Header: /root/leakn64/depot/rf/hw/flif/xilinx/RAM32X1D.v,v 1.1 2003/08/20 23:46:55 berndt Exp $
/*
FUNCTION : 32x1 Dual Port Static RAM with synchronous write capability
*/
`timescale 100 ps / 10 ps
module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
parameter INIT = 32'h00000000;
output DPO, SPO;
input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
reg mem [31:0];
reg [5:0] count;
wire [4:0] adr;
wire [4:0] dpr_adr;
wire d_in, wclk_in, we_in;
buf b_d (d_in, D);
buf b_wclk (wclk_in, WCLK);
buf b_we (we_in, WE);
buf b_a4 (adr[4], A4);
buf b_a3 (adr[3], A3);
buf b_a2 (adr[2], A2);
buf b_a1 (adr[1], A1);
buf b_a0 (adr[0], A0);
buf b_d4 (dpr_adr[4], DPRA4);
buf b_d3 (dpr_adr[3], DPRA3);
buf b_d2 (dpr_adr[2], DPRA2);
buf b_d1 (dpr_adr[1], DPRA1);
buf b_d0 (dpr_adr[0], DPRA0);
buf b_spo (SPO, spo_int);
buf b_dpo (DPO, dpo_int);
buf b_spo_int (spo_int, mem[adr]);
buf b_dpo_int (dpo_int, mem[dpr_adr]);
initial begin
for (count = 0; count < 32; count = count + 1)
mem[count] <= INIT[count];
end
always @(posedge wclk_in) begin
if (we_in == 1'b1)
mem[adr] <= d_in;
end
specify
if (WE)
(WCLK => SPO) = (1, 1);
if (WE)
(WCLK => DPO) = (1, 1);
(A4 => SPO) = (1, 1);
(A3 => SPO) = (1, 1);
(A2 => SPO) = (1, 1);
(A1 => SPO) = (1, 1);
(A0 => SPO) = (1, 1);
(DPRA4 => DPO) = (1, 1);
(DPRA3 => DPO) = (1, 1);
(DPRA2 => DPO) = (1, 1);
(DPRA1 => DPO) = (1, 1);
(DPRA0 => DPO) = (1, 1);
endspecify
endmodule