RAMB4_S2.v
4.22 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
// $Header: /root/leakn64/depot/rf/hw/flif/xilinx/RAMB4_S2.v,v 1.1 2003/08/20 23:46:56 berndt Exp $
/*
FUNCTION : 4x2 Block RAM with synchronous write capability
*/
`timescale 100 ps / 10 ps
module RAMB4_S2 (DO, ADDR, CLK, DI, EN, RST, WE);
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
output [1:0] DO;
reg d0_out, d1_out;
input [10:0] ADDR;
input [1:0] DI;
input EN, CLK, WE, RST;
reg [4095:0] mem;
reg [8:0] count;
wire [10:0] addr_int;
wire [1:0] di_int;
wire en_int, clk_int, we_int, rst_int;
tri0 GSR = glbl.GSR;
always @(GSR)
if (GSR)
begin
assign d0_out = 0;
assign d1_out = 0;
end
else
begin
deassign d0_out;
deassign d1_out;
end
buf b_do_out0 (DO[0], d0_out);
buf b_do_out1 (DO[1], d1_out);
buf b_addr_0 (addr_int[0], ADDR[0]);
buf b_addr_1 (addr_int[1], ADDR[1]);
buf b_addr_2 (addr_int[2], ADDR[2]);
buf b_addr_3 (addr_int[3], ADDR[3]);
buf b_addr_4 (addr_int[4], ADDR[4]);
buf b_addr_5 (addr_int[5], ADDR[5]);
buf b_addr_6 (addr_int[6], ADDR[6]);
buf b_addr_7 (addr_int[7], ADDR[7]);
buf b_addr_8 (addr_int[8], ADDR[8]);
buf b_addr_9 (addr_int[9], ADDR[9]);
buf b_addr_10 (addr_int[10], ADDR[10]);
buf b_di_0 (di_int[0], DI[0]);
buf b_di_1 (di_int[1], DI[1]);
buf b_en (en_int, EN);
buf b_clk (clk_int, CLK);
buf b_we (we_int, WE);
buf b_rst (rst_int, RST);
initial
begin
for (count = 0; count < 256; count = count + 1)
begin
mem[count] <= INIT_00[count];
mem[256 * 1 + count] <= INIT_01[count];
mem[256 * 2 + count] <= INIT_02[count];
mem[256 * 3 + count] <= INIT_03[count];
mem[256 * 4 + count] <= INIT_04[count];
mem[256 * 5 + count] <= INIT_05[count];
mem[256 * 6 + count] <= INIT_06[count];
mem[256 * 7 + count] <= INIT_07[count];
mem[256 * 8 + count] <= INIT_08[count];
mem[256 * 9 + count] <= INIT_09[count];
mem[256 * 10 + count] <= INIT_0A[count];
mem[256 * 11 + count] <= INIT_0B[count];
mem[256 * 12 + count] <= INIT_0C[count];
mem[256 * 13 + count] <= INIT_0D[count];
mem[256 * 14 + count] <= INIT_0E[count];
mem[256 * 15 + count] <= INIT_0F[count];
end
end
always @(posedge clk_int)
begin
if (en_int == 1'b1)
if (rst_int == 1'b1)
begin
d0_out <= 0;
d1_out <= 0;
end
else
if (we_int == 1'b1)
begin
d0_out <= di_int[0];
d1_out <= di_int[1];
end
else
begin
d0_out <= mem[addr_int * 2];
d1_out <= mem[addr_int * 2 + 1];
end
end
always @(posedge clk_int)
begin
if (en_int == 1'b1 && we_int == 1'b1)
begin
mem[addr_int * 2] <= di_int[0];
mem[addr_int * 2 + 1] <= di_int[1];
end
end
specify
(CLK *> DO) = (1, 1);
endspecify
endmodule