nvram_test.c
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/**********************************************
*
* nvram_test.c
*
* Collection of Virage NVRAM tests for IOSIM
*
**********************************************/
#include <PR/ultratypes.h>
#include "PR/bcp.h"
#include "PR/bbnvram.h"
#include "ultra64.h"
#include "os_bb.h"
#include "bcp.h"
#include "nu64sys.h"
#include "graph.h"
/*
#include "simipc.h"
#include "iomap.h"
#include "bcptest.h"
#include "bcp_util.h"
#include "simipc.h"
#include "iotest.h"
#include "nvram_test.h"
#include "nvram.h"
*/
#include "nvram_util.h"
#define V2_DEFAULT_VALUE 0x0
/*
* Temporary storage which should match the contents for the most
* recent store
*/
static int virage_data[64];
static int seed = 0x01234578;
static unsigned int myrand(){
seed = 0x343fd *seed + 0x269ec3;
return ((seed) & 0xffffffff);
}
int nms_store_test(int sysclk_scale, int ctrl_reg, int size, int test_num)
{
int x;
int i;
int array_addr = ctrl_reg & 0xffff0000;
int sysclk = get_sys_clk_ns(sysclk_scale);
/*
* Make sure the NMS is not bypassed
*/
IO_WRITE(ctrl_reg, 0x0);
/*
* This should be set to give 1uSec. It uses sysclock as input. Wait
* a little afterwards to make sure a few clocks of time-base go through
*/
IO_WRITE(MI_SEC_VTIMER_REG, 1000/SYSCLK_NS + 1);
for (i =0; i < (4*160000)/sysclk; i++){
;
}
/*
BCP_STALL((4 * 160000)/sysclk);
*/
/*
* Wait for Charge pump to exit PORST
*/
x = IO_READ(ctrl_reg);
if (x & VIRAGE_CTRL_CP_PORST) {
for (i =0; i < (sysclk_scale*20000)/sysclk; i++){
;
}
/*
BCP_STALL(sysclk_scale *20000/sysclk);
*/
for (i =0; i < (sysclk_scale*20000)/sysclk; i++){
;
}
x = IO_READ(ctrl_reg);
if (x & VIRAGE_CTRL_CP_PORST) {
sprintf(buf, "PORST not done ctrl_reg = %08x", ctrl_reg);
printstr(white, 3, 7, buf);
osWritebackDCacheAll();
return FAIL;
}
}
/*
sprintf(buf, "PORST done ctrl_reg = %08x", ctrl_reg);
printstr(white, 3, 2, buf);
osWritebackDCacheAll();
*/
x = IO_READ(ctrl_reg);
if ((x & VIRAGE_CTRL_NMS_READY) == 0) {
sprintf(buf, "NMS Not Ready");
printstr(white, 3, 4, buf);
osWritebackDCacheAll();
return FAIL;
}
/*
sprintf(buf, "NMS Ready");
printstr(white, 3, 4, buf);
osWritebackDCacheAll();
*/
/*
* Fill the SRAM with random stuff
*/
seed = osGetCount();
for (i=0; i<size; i++) {
virage_data[i] = myrand();
IO_WRITE(array_addr+(i<<2), virage_data[i]);
x = IO_READ(array_addr+(i<<2));
if (x != virage_data[i]) {
sprintf(buf, "SRAM read write failure");
printstr(white, 3, 6, buf);
osWritebackDCacheAll();
return FAIL;
}
}
switch(test_num){
case 0:
/*
* store and recall with default values
*/
if (nms_store_default(ctrl_reg) != PASS) {
return FAIL;
}
break;
#if 0
case 1:
/*
* store and recall with typical values
*/
if (nms_store(ctrl_reg, NMS_STORE_PW_10MS, NMS_VPPLEVEL_7P4V, NMS_VPPMAX_8P0V, NMS_VPPDELTA_400MV, NMS_NMAX_2, 7) != PASS) {
return FAIL;
}
break;
#endif
}
/*
* remove old data
*/
for (i=0; i<size; i++) {
IO_WRITE(array_addr+(i<<2), 0);
x = IO_READ(array_addr+(i<<2));
if (x != 0) {
sprintf(buf, "SRAM clear failure");
printstr(white, 3, 13, buf);
osWritebackDCacheAll();
return FAIL;
}
}
if (nms_recall(sysclk_scale, ctrl_reg) != PASS) {
sprintf(buf, "SRAM recall failure");
printstr(white, 3, 13, buf);
osWritebackDCacheAll();
return FAIL;
}
/*
* Check all values
*/
for (i=0; i<size; i++) {
x = IO_READ(array_addr+(i<<2));
if (x != virage_data[i]) {
sprintf(buf, "SRAM recall failure");
printstr(white, 3, 2, buf);
osWritebackDCacheAll();
return FAIL;
}
}
return PASS;
}