vi16bar.c
1.52 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
#include "cpusim.h"
#define CMEM_WORD (*(vu32*)K0BASE)
#define UMEM_WORD (*(vu32*)K1BASE)
#define CMEM64_WORD (*(vu32*)PHYS_TO_K0(DDRRAM64_START))
#define UMEM64_WORD (*(vu32*)PHYS_TO_K1(DDRRAM64_START))
#define CNONMEM_WORD (*(vu32*)PHYS_TO_K0(PI_BUFFER_BASE_REG))
#define UNONMEM_WORD (*(vu32*)PHYS_TO_K1(PI_BUFFER_BASE_REG))
#define WIDTH 320
#define HEIGHT 240
#define FRAME_BUFFER 0x18f800
#define WORDS_PER_LINE ((WIDTH*2) / 4)
unsigned int bars[8] = { 0x7BDE7BDE, //grey f f f 0
0x7BD07bd0, //yellow f f 8 0
0x0, //black 0 0 0 0
0x7BC07bc0, //cyan f f 0 0
0x07C007C0, //green 0 1f 0 0
0xF800F800, //Red 1f 0 0 0
0x003e003e, //blue 0 0 1f 0
0x781E781E //magenta 0f 0 0f 0
};
main() {
int i, j, k;
unsigned int mask, addr;
void (*f0)(void);
static void run(void);
vu32 *p;
if (((getcp0reg(C0_CONFIG)&CONFIG_EC) >> 28) != 1)
IO_WRITE(MI_CTRL_REG, MI_CTRL_HARD_RESET|MI_CTRL_DIV_MODE_1_5);
test_preamble();
initICache();
initDCache();
init_ddr();
p = (vu32 *) (K0BASE + FRAME_BUFFER);
for (i=0; i<HEIGHT; i++) {
for (j=0; j<8; j++) {
for (k=0; k<WORDS_PER_LINE/8; k++)
*p++ = bars[j];
}
}
message("DDR access test\n");
DBG_JTAG_PASS("DDR access test passed\n");
test_postamble();
return 0;
}