bcp_ai.tst
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//****************************************************************************
//
// File: ai.tst
// Test file for Audio Interface (AI)
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//****************************************************************************
//****************************************************************************
// Configure DDR
//
//t 0200 00000000 00000000 00000000 00000000
k 1
//****************************************************************************
// Init RDRAM with pattern data (rdram_addr, nbytes, pattern_key)
t 0013 00000000 00000040 87654321 00000000
// Init Video Interface (VI) to get proper video clock signal into AI
t 0102 04400000 00000000 00000000 00000000
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// Set DAC rate
//t 0102 04500010 00000086 00000000 00000000
// Set bit rate
//t 0102 04500014 00000001 00000000 00000000
// Enable DMA
//t 0102 04500008 00000001 00000000 00000000
//****************************************************************************
// Test AI DMA: dram_address, nbytes
//****************************************************************************
// DMA 20 Bytes (RDRAM -> AI) -> SHOULD PASS
// Note: Address and data must be 8-byte aligned
//
t 0043 00000000 00000014 00000000 00000000
// Perform a CPU memory read
t 0100 00000008 00000000 00000000 00000000
// Disable DMA
t 0104 0450000c 40000000 00000001 00000000
t 0102 04500008 00000000 00000000 00000000
// Perform a CPU memory write and compare
t 0103 00000010 01010101 01010101 00000000
// Check for interrupt bit set (bit 2)
t 0104 04300008 00000004 00000000 00000000
// Now, test for DMA busy bit
//t 0046 40000000 00000000 00000000 00000000
t 0104 0450000c 40000000 00000001 00000000
// Enable DMA
t 0102 04500008 00000001 00000000 00000000
// Check for interrupt bit set (bit 2)
t 0104 04300008 00000004 00000000 00000000
// Clear interrupt bit
t 0102 0450000C 00000000 00000000 00000000
// Check for interrupt bit reset (bit 2)
t 0104 04300008 00000004 00000001 00000000
// DMA again
t 0043 00000008 00000008 00000000 00000000
// Check for busy bit
t 0104 0450000c 40000000 00000001 00000000
//****************************************************************************
// Here, we stall in verilog for X cycles to make sure that data is shifted
// out to Audio DAC
// Wait for around 3000 cycles
t 0014 00000300 00000000 00000000 00000000
//****************************************************************************
// Init Ai (DAC rate, bit rate, DMA enable)
//t 003 00000090 00000002 00000000 00000000
//****************************************************************************
// DMA 16 Bytes (RDRAM -> AI) -> SHOULD PASS
// Note: Address and data must be 8-byte aligned
//
t 0043 00000020 00000010 00000000 00000000
// Here we're reading length register until it's empty
//t 0045 04500004 00000000 00000000 00000000
// Perform a CPU memory read
t 0100 00000010 00000000 00000000 00000000
// Disable DMA
t 0102 04500008 00000000 00000000 00000000
// Perform a CPU memory write and compare
t 0103 00000020 01010101 01010101 00000000
// Check for interrupt bit set (bit 2)
t 0104 04300008 00000004 00000000 00000000
// Now, test for DMA busy bit
//t 0104 0450000c 40000000 00000001 00000000
// Enable DMA
t 0102 04500008 00000001 00000000 00000000
// Check for interrupt bit set (bit 2)
t 0104 04300008 00000004 00000000 00000000
// Clear interrupt bit
t 0102 0450000C 00000000 00000000 00000000
// Check for interrupt bit reset (bit 2)
t 0104 04300008 00000004 00000001 00000000
// Check for busy bit
t 0104 0450000c 40000000 00000001 00000000
//****************************************************************************
// Here, we stall in verilog for X cycles to make sure that data is shifted
// out to Audio DAC
// Wait for around 4000 cycles
t 0014 00000400 00000000 00000000 00000000
//****************************************************************************
// Test AI length counter: repeatdly start a dma with a length and
// check for the count to decrement to next bit position
// relies on rdram data being previously loaded
// Init Video Interface (VI) to get proper video clock signal into AI
t 0102 04400000 00000000 00000000 00000000
//****************************************************************************
// ** test msb bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00020000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 0001fff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00010000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 0000fff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00008000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00007ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00004000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00003ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00002000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00001ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00001000 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000ff8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000800 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 000007f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000400 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 000003f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000200 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 000001f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000100 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 000000f8 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000080 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000078 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000040 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000038 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000020 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000018 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000010 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000008 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
//** test next bit of counter
// Configure Ai (DAC rate, bit rate) with DMA enable
t 003 00000086 00000001 00000000 00000000
// start ai dma of specified length
t 0048 00000000 00000008 00000000 00000000
// spin on length decrementing to specified value -> SHOULD PASS
t 0049 00000000 00000000 00000000 00000000
// soft reset (bit rate 0) to stop the dma in progress
t 003 00000000 00000000 00000000 00000000
// clear ai interrupt
t 102 0450000c 0 0 0
//** note will need to restore dac counter for any further tests
//****************************************************************************
// QUIT
//****************************************************************************
//q
k 0