bcp_sp.tst
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//****************************************************************************
//
// File: ai.tst
// Test file for RSP
//
// $Revision: 1.4 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
// Common Test IDs:
// ================
// 0 - rdramConfig
// 13 - rdramInit
// 60 - SpTestReg
// 61 - SpTestIoRead
// 62 - SpTestIoWrite
// 63 - SpTestDma
// 64 - SpDumpData
// 65 - SpCompareData
// 66 - SpTestStatus
// 67 - SpTestDmaPg
// 101 - MemReadCompare
// 102 - MemWrite
// 103 - MemWriteCompare
// 106 - MemCompare
//
// DMEM Address: 0x04000000 - 0x04000FFF
// IMEM Address: 0x04001000 - 0x04001FFF
//
//****************************************************************************
//****************************************************************************
//
//t 0200 00000000 00000000 00000000 00000000
k 1
//****************************************************************************
// Store data into RDRAM -> SHOULD PASS
// Test Single RDRAM R/W (4-byte): address, data, type
//
t 0013 00000000 00000040 12340000 00000000
//****************************************************************************
// R/W data into SP registers -> SHOULD PASS
// Test Reg: address, data
// Initialize IMEM with valid instructions:
// noop
// jump to location 0
// noop
// noop
t 0062 04001000 00000000 00000001 00000000
t 0062 04001004 08000000 00000001 00000000
t 0062 04001008 00000000 00000001 00000000
t 0062 0400100c 00000000 00000001 00000000
// Initialize PC to 0
t 0103 04080000 00000000 00000000 00000000
// Write and read back status reg (clear halt)
t 0103 04040010 00000001 00000000 00000000
// Write and read back status reg (set halt)
t 0103 04040010 00000002 00000001 00000000
// Write to I/DMEM reg
//t 0060 04040000 00001234 00000001 00000000
// Write to DRAM reg
//t 0060 04040004 00203040 00000001 00000000
//****************************************************************************
// Test interrupt -> SHOULD PASS
// Write to MI interrupt mask: set SP mask
t 0102 0430000C 00000002 00000000 00000000
// Write to SP status reg: set intr
t 0102 04040010 00000010 00000000 00000000
// Read from MI interrupt reg: SP should be set
t 0101 04300008 00000001 00000000 00000000
// Write and read back SP status reg: clear intr, but halt should still be set
t 0103 04040010 00000008 00000001 00000000
// Read from MI interrupt reg: SP should be clear
t 0101 04300008 00000000 00000000 00000000
// Write to status reg (set halt) and read back status
t 0103 04040010 00000002 00000001 00000000
// Write to PC
// Note that PC is 12-bit and least 2 bits are always 0 (word-aligned)
t 0103 04080000 0000abcd 00000bcc 00000000
t 0103 04080000 00008bc4 00000bc4 00000000
t 0103 04080000 00000F22 00000f20 00000000
t 0103 04080000 000008f0 000008f0 00000000
//****************************************************************************
// IO R/W to D/IMEM -> SHOULD PASS
t 0062 04000000 12345678 00000001 00000000
t 0062 04000004 01020304 00000001 00000000
t 0062 04000008 87654321 00000001 00000000
t 0062 04000FF0 11223456 00000001 00000000
t 0062 04000FF8 10203040 00000001 00000000
t 0062 04000FFC fedcba98 00000001 00000000
t 0062 04001000 12345678 00000001 00000000
t 0062 04001004 01020304 00000001 00000000
t 0062 04001008 87654321 00000001 00000000
t 0062 04001FF0 11223456 00000001 00000000
t 0062 04001FF8 10203040 00000001 00000000
t 0062 04001FFC fedcba98 00000001 00000000
//****************************************************************************
// Test single-step
//
//****************************************************************************
// Test SP DMA
// Parameters: direction (1=from_RDRAM, 2=to_RDRAM),
// D/IMEM address, RDRAM address,
// length (skip[12], count[8], len[12])
// Note: skip only occurs on the RDRAM, not on D/IMEM
//****************************************************************************
// DMA 20 Bytes (RDRAM -> SP D/IMEM) -> SHOULD PASS
//
// DMEM Address: 0x04000000 - 0x04000FFF
// IMEM Address: 0x04001000 - 0x04001FFF
t 0063 00000001 04000000 00000000 00001010
t 0063 00000002 04000000 00000100 00000020
t 0063 00000001 04001000 00000000 00001010
t 0063 00000002 04001000 00010200 00000010
t 0063 00000002 04001000 00010300 00001010
t 0063 00000001 04001100 00000000 00801020
t 0063 00000002 04001100 00010400 00801010
//****************************************************************************
// Check for DMA busy/full bits (2 and 3) to be cleared
t 0104 04040010 0000000c 00000001 00000000
//****************************************************************************
// Here, we compare D/IMEM with RDRAM (src, dst, nbytes, failExpected)
t 0065 04000000 00000000 00000020 00000000
t 0065 04000000 00000100 00000020 00000000
t 0065 04001000 00000000 00000020 00000000
t 0065 04001000 00010200 00000010 00000000
t 0065 04001100 00010300 00000020 00000000
t 0065 04001120 00000028 00000020 00000000
t 0065 04001100 00010400 00000010 00000000
t 0065 04001110 00010418 00000010 00000000
//****************************************************************************
// Here, we dump out RDRAM (address, nwords)
t 0106 00000000 0000000a 00000000 00000000
t 0106 000000fc 0000000a 00000000 00000000
t 0106 000101fc 0000000a 00000000 00000000
t 0106 000102fc 0000000c 00000000 00000000
t 0106 000103fc 0000000c 00000000 00000000
//****************************************************************************
// QUIT
//****************************************************************************
//q
k 0