venc_ntsc_trap.tst
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//****************************************************************************
//
// File: venc_ntsc_trap.tst
// Test file for Encoder
//
// NOTE: input vclock should have 69841 ps period: sim.ipc +vclk=69841
//****************************************************************************
// Keep alive socket
k 1
vi_snoop 1
// Configure RDRAM
t 0200 00000000 00000000 00000000 00000000
// PLL configure for NTSC: n=34, m=5, p=2, S=1, VNTPL=1, power up dac
// VTRAP is set to 1 for this test
t 103 0x04300030 0x00594245 0x00594245 0x0
t 103 0x04300030 0x00594244 0x00594244 0x0
// Wait 37 uSec for PLL clock to come out
t 014 0E80 0 0 0
// Now reset the encoder using the test mode control
// and take vi out of reset
t 103 0x04300030 0x02d94244 0x02d94244 0x0
t 014 10 0 0 0
t 103 0x04300030 0x02594244 0x02594244 0x0
t 014 30 0 0 0
t 103 0x04300030 0x02d94244 0x02d94244 0x0
t 014 10 0 0 0
t 103 0x04300030 0x02594244 0x02594244 0x0
t 014 10 0 0 0
// Fill DRAM with data
// 700 is Luma ramp
t 0700 0x1000 280 0 0
// 701 is Color bars
t 0701 0x1a00 280 0 0
t 0700 0x2400 280 0 0
t 0701 0x2e00 280 0 0
t 0701 0x3800 280 0 0
// Read VI_CTRL, make sure is zeroed out
t 0103 04400000 00000000 00000000 00000000
// Write-Read VI_ORIGIN
t 0103 04400004 00001000 00001000 00000000
// Write-Read VI_WIDTH
t 0103 04400008 00000280 00000280 00000000
// Write-Read VI_V_INT
t 0103 0440000c 000003ff 000003ff 00000000
// Write-Read VI_BURST
t 0103 04400014 03e22239 03e22239 00000000
// Write-Read VI_V_SYNC
t 0103 04400018 00000028 00000028 00000000
// Write-Read VI_H_SYNC
t 0103 0440001c 00000c15 00000c15 00000000
// Write-Read VI_LEAP
t 0103 04400020 0c150c15 0c150c15 00000000
// Write-Read VI_H_START
t 0103 04400024 006c02ec 006c02ec 00000000
// Write-Read VI_V_START
t 0103 04400028 00050025 00050025 00000000
// Write-Read VI_V_BURST
t 0103 0440002c 00050025 00050025 00000000
// Write-Read VI_X_SCALE
t 0103 04400030 00000400 00000400 00000000
// Write-Read VI_Y_SCALE
t 0103 04400034 00000400 00000400 00000000
// Write-Read VI_CTRL
t 0103 04400000 00003303 00003303 00000000
// Write VI_V_CURRENT
t 0102 04400010 00000000 00000000 00000000
// Read VI_V_CURRENT
t 0100 04400010 00000000 00000000 00000000
// Loop until we hit line number 0xc
t 0107 04400010 ffffffff 0000000c 00000000
//****************************************************************************
// QUIT
//****************************************************************************
k 0
q