entry.s
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#include <regdef.h>
#include <asm.h>
#include <PR/R4300.h>
#include <PR/bcp.h>
#include "boot.h"
// XXX: t7 is reserved for use in TRACE macros, do not use.
.text
.align 2
.set noreorder
.globl __entry
__entry:
# this must be done before any lw or sw
mtc0 zero, C0_WATCHLO
mtc0 zero, C0_WATCHHI
# poll virage2 ctrl for ready bit
la t0, PHYS_TO_K1(VIRAGE2_CTRL_REG)
virage2_poll:
lw t1, 0(t0)
and t2, t1, VIRAGE_CTRL_NV_RCREADY
beqz t2, virage2_poll
nop
#
# checksum over virage flash 2 (read-only)
#
# compute checksum
la t0, PHYS_TO_K1(VIRAGE2_RAM_START)
la t1, PHYS_TO_K1(VIRAGE2_RAM_END)-4
move t4, zero
virage2_checksum:
lw t3, 0(t0)
addu t4, t3
bltu t0, t1, virage2_checksum
addu t0, 4
# compare checksum
beq t4, VIRAGE2_CHECKSUM, virage2_good
nop
# bad checksum
JUMP_HANDLER
virage2_good:
# first boot-code patch entry point into internal flash.
# register t0 holds the address to jump to in isram,
# so if no patch is needed the flash instructions
# will be:
# jr t0
# nop
la t0, patch1_return
j PHYS_TO_K1(VIRAGE2_BOOT_PATCH2_START)
nop
patch1_return:
# take IDE out of reset so future TRACEs will work
li t0, PHYS_TO_K1(PI_IDE_CONFIG_REG)
lw t1, 0(t0)
and t1, ~PI_IDE_CONFIG_RESET
sw t1, 0(t0)
TRACE_VAL(0x1)
# copy ROM code to IRAM
# t0: dst
# t2: src
# t1: end
la t0, PHYS_TO_K1(INTERNAL_RAM_START)
la t2, __s_la_text
la t1, __e_text
copy_rom_to_iram:
lw t3, 0(t2) # the rom instruction
sw t3, 0(t0) # save to iram
addu t0, 4
bltu t0, t1, copy_rom_to_iram
addu t2, 4
# allow patch of copied code from internal flash.
# register t0 holds the address to jump to in isram,
# so if no patch is needed the flash instructions
# will be:
# jr t0
# nop
la t0, __start
j PHYS_TO_K1(VIRAGE2_BOOT_PATCH1_START)
nop