/*
 *  dbp.c   BB debug board parallel port library
 *
 * See bbplayer/tools/jtag for an example of an app that uses this
 * library and libjtag to perform JTAG functions via the parallel port.
 *
 * This lib is currently only operational for using JTAG
 * via the parallel port.
 *
 * There are experimental routines at the end of this file that 
 * were intended to be completed for use in interfacing via EPP
 * to communicate with either a tiny monitor (like in the diags app)
 * or Rmon for a printf server.
 *
 * Those routines are not currently used and are probably only useful
 * for reference when implementing the real routines for
 * communicating with tinymon or rmon via parallel port.
 *
 * JTAG uses dbp_jtag_write, dbp_jtag_read, dbp_jtag_wait as callbacks
 * from the libjtag code.  It is fully supported without the 
 * experimental routines at the end of the file.
 *
 * I started out thinking block writes/reads would be useful, but
 * the actual protocols with the BB require handshaking for every 32 bit
 * transfer.
 *
 * It may only be useful for this lib to provide the protocol
 * for transferring 32 bit packets using the debug board parallel port.
 *
 * You could let an app take care of the actual TinyMon OR Rmon protocol
 * and mutiple word transmisions.
 *
 */


#include <sys/types.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <netinet/in.h>
#include <errno.h>
#include <fcntl.h>
#include <stdlib.h>
#include <stdio.h>
#define __USE_GNU
#include <unistd.h>
#include <string.h>
#include <getopt.h>
#include <sys/socket.h>
#include <sys/un.h>
#include <sys/io.h>
#include "dbp.h"
#include "dbp_sim.h"

#define	EPP_JTAG
//#undef EPP_JTAG

//#define PAR_IO_DIRECT
#ifdef PAR_IO_DIRECT

#define PAR_NAME_LEN 64
int spp_data_port, spp_sts_port, spp_ctrl_port;
int epp_data_port, epp_addr_port;

int epp_open(const char *dev)
{
	int spp=-1, epp=-1, len, len1; 
	char *dev_name;
	char par_name[PAR_NAME_LEN]="/proc/sys/dev/parport/parport0/base-addr";
	char s_addr[PAR_NAME_LEN];
	FILE *f;

	dev_name=strstr(dev, "parport");
	if (dev_name == NULL) 
		fprintf(stderr, "Invalid parport device name: %s", dev);
	len1=strlen("parport");
	len=strlen("/proc/sys/dev/parport/parport");
	par_name[len] = dev_name[len1];

	if (iopl(3) < 0) {
		perror("connect");
		return -1;
	}

	if ((f = fopen(par_name, "rb")) == NULL) {
		perror("Parport proc file cannot opened");
		return -1;
	}
	fgets(s_addr, PAR_NAME_LEN, f);
	fclose(f);

	sscanf(s_addr, "%d %d", &spp, &epp);
	if ((spp <=0) || (spp >= 65536) || (epp <= 0) || (epp >=65536)) {
		fprintf(stderr, "Invalid parport base %d %d", spp, epp);
		return -1;
	}
	
	spp_data_port = spp;
	spp_sts_port = spp + 1;
	spp_ctrl_port = spp + 2;

	epp_data_port = epp + 4;
	epp_addr_port = epp + 3;

	return 1;
}
#endif

static int set_jtag_transport();
static int dbp_jtag_write(transport_specific_param *p, int x);
static int dbp_jtag_read(transport_specific_param *p);
static int dbp_jtag_wait(transport_specific_param *p, int cycle);

int dbp_set_protocol(dbp_Protocol protocol);
typedef struct {
    int          fd;
    dbp_Protocol protocol;
    char        *protocol_str;
    int          mode;   /* IEEE1284_MODE_??? */
    char        *mode_str;
    int		epp;
} dbp_state;

static dbp_state dbp = { -1 };

static char *protocol_str[] = { "dbp_JTAG", "dbp_TinyMon", "dbp_Rmon", "dbp_MUX" };

int dbp_verbose = 0;         /* set by clients of the library */


int
dbp_open(dbp_Protocol protocol, const char* devname_or_null)
{
    const char *ppname;

    if (getenv("DBP_EPP")) dbp.epp = 1;
    if (protocol == dbp_SIM) { /* USE Verilog Simulator */
        dbp.protocol = dbp_SIM;
        set_jtag_transport();
        dbp.fd = open_simulator_sock();
        if (dbp.fd < 0) {
            fprintf(stderr, "\n Cannot open socket for simulator port");
            return -1;
        }
        return dbp.fd;
    } else if (protocol == dbp_MUX) {
	struct sockaddr_un sa;
	if ((dbp.fd = socket(PF_UNIX, SOCK_STREAM, 0)) < 0)
	    return dbp.fd;
	sa.sun_family = AF_UNIX;
	strncpy(sa.sun_path, devname_or_null, sizeof sa.sun_path);
	if ((connect(dbp.fd, (struct sockaddr*)&sa, sizeof sa)) < 0) {
	     perror("connect");
	     return -1;
	}
	dbp.protocol = dbp_MUX;

        set_jtag_transport();
	return dbp.fd;
    }

    if(dbp.fd > 0) {
        fprintf(stderr,"\n dbp_open: port already open ?  dbp fd: %d\n\n", dbp.fd);
        return -1;
    }

    if(devname_or_null)
        ppname = devname_or_null;
    else
        ppname = "/dev/parport0";

#ifdef PAR_IO_DIRECT
    if ((dbp.fd = epp_open(ppname)) == -1) {
#else
    if ((dbp.fd=open(ppname,O_RDWR)) == -1) {
#endif
        fprintf(stderr,"\n dbp_open: Unable to open %s\n", ppname);
        perror ("\n\t open");
        goto err3;
    }

    if(dbp_set_protocol(protocol)) {
        fprintf(stderr,"\n dbp_open: dbp_set_protocol failed\n");
        goto err1;
    }

    return dbp.fd;

err1:

#ifndef PAR_IO_DIRECT
    if(ioctl(dbp.fd, PPRELEASE)) {
        perror ("\n\t dbp_open: PPRELEASE");
    }
#endif

    if(close(dbp.fd)) {
        perror ("\n\t dbp_open: close");
    }
err3:
    dbp.fd = -1;
    return -1;
}

/*
 * claim or release pp control
 */
int
dbp_cr(int claim)
{
#ifndef PAR_IO_DIRECT
	return(ioctl(dbp.fd, claim? PPCLAIM : PPRELEASE));
#else 
	return 0;
#endif
}

int
dbp_close()
{
    int err = 0;

    if(dbp.fd <= 0) {
        fprintf(stderr,"dbp_close: device not open\n");
        return -1;
    }

#ifdef PAR_IO_DIRECT
    if ((dbp.protocol !=  dbp_SIM) && (dbp.protocol !=  dbp_MUX))
	return 0; 
#endif

    if (dbp.protocol == dbp_SIM)
	keep_alive_sock(dbp.fd, 0);

    if(dbp.protocol != dbp_SIM)
    	dbp_cr(0);

    if(close(dbp.fd)) {
        perror ("\n\t close");
        err = 1;
    }
    dbp.fd = -1;
    return err ? -1 : 0;
}

/*
 * fpga micro-code;
 */
static u_char dbp_fpga_code[] = {
#include "dbx.c"
};

/*
 * check and possibly configure debug board fpga;
 * returns 0 for failure;
 */
static int
dbp_config_fpga(void)
{
	u_int sts, mask, ctrl, data;
	int n, err = 0;

	/*
	 * read status of fpga DONE bit on SPP nFault signal;
	 * nFault 0=not configured, 1=configured;
	 */
	sts = 0;
#ifdef  PAR_IO_DIRECT
	sts = inb(spp_sts_port);
#else
	if(ioctl(dbp.fd, PPRSTATUS, &sts)) {
		perror(" dbp_config_fpga[1]: read DONE status");
		return(0);
	}
#endif
	/*
	 * if PError (USR1) or Select (USR3) are 1,
	 * then we have nothing plugged into the pp,
	 * or the fpga is not configured;
	 */
	mask = PARPORT_STATUS_PAPEROUT
		| PARPORT_STATUS_SELECT
		| PARPORT_STATUS_ERROR;
	if((sts & mask) == 0)
		return(1);
	/*
	 * configuration has to be done in SPP mode,
	 * because there is no ACK coming back;
	 */
#ifndef PAR_IO_DIRECT
	dbp.mode = IEEE1284_MODE_BYTE;
	if(ioctl(dbp.fd, PPSETMODE, &dbp.mode)) {
		perror(" dbp_config_fpga[2]: set SPP mode");
		return(0);
	}
#endif
	/*
	 * drive nInit=0, nDstb=1, nAstb=1, nWrite=0;
	 * wait 100us for fpga to enter init mode;
	 */
	ctrl = PARPORT_CONTROL_STROBE;
#ifndef PAR_IO_DIRECT
	err = ioctl(dbp.fd, PPWCONTROL, &ctrl);
#else
	outb(ctrl, spp_ctrl_port);
#endif
	usleep(100);

	ctrl |= PARPORT_CONTROL_INIT;
#ifndef PAR_IO_DIRECT
	err |= ioctl(dbp.fd, PPWCONTROL, &ctrl);
#else
	outb(ctrl, spp_ctrl_port);
#endif
	if(err) {
		perror(" dbp_config_fpga[3]: init start");
		return(0);
	}
	usleep(200);

	/*
	 * output configuration data;
	 * create one data strobe per byte;
	 * can toggle as fast as PC allows;
	 * ignore BUSY for < 50Mhz;
	 * remember: bit D0 is MSB;
	 * stop on first error;
	 */
	err = 0;
	for(n = 0; !err && n < sizeof(dbp_fpga_code); n++) {
		data = dbp_fpga_code[n];
#ifndef PAR_IO_DIRECT
		err |= ioctl(dbp.fd, PPWDATA, &data);
#else
		outb(data, spp_data_port);
#endif
		ctrl |= PARPORT_CONTROL_AUTOFD;
#ifndef PAR_IO_DIRECT
		err |= ioctl(dbp.fd, PPWCONTROL, &ctrl);
#else
		outb(ctrl, spp_ctrl_port);
#endif
		ctrl &= ~PARPORT_CONTROL_AUTOFD;
#ifndef PAR_IO_DIRECT
		err |= ioctl(dbp.fd, PPWCONTROL, &ctrl);
#else
		outb(ctrl, spp_ctrl_port);
#endif
	}
	/*
	 * DONE of fpga should have gone H;
	 * if not, then there is a config problem;
	 */
#ifndef PAR_IO_DIRECT
	err |= ioctl(dbp.fd, PPRSTATUS, &sts);
#else
	sts = inb(spp_sts_port);
#endif
	if(err | !(sts & PARPORT_STATUS_ERROR)) {
		fprintf(stderr, "dbp_config_fpga[4]: failed\n"); 
		return(0);
	}
	return(1);
}

/*
 * read/write the control register;
 * this is using address cycles;
 * writes:
 *	10ww_wwww set write pointer to w*32 bytes;
 *	11rr_rrrr set read pointer to r*32 bytes;
 *	01xx_xxxx reset host side;
 *	001x_xJJJ set host->bb request;
 *	000x_xxx1 set host->bb request;
 *	000x_xx1x set host->bb ack;
 *	000x_x1xx clear host<-bb request;
 *	000x_1xxx clear host<-bb ack;
 * reads:
 *	xxxx_xxx1 outgoing request;
 *	xxxx_xx1x outgoing ack;
 *	xxxx_x1xx incoming request;
 *	xxxx_1xxx incoming ack;
 * returns return code of read() or write(),
 * or -1 for error;
 */
int
dbp_ctrl(int wr, u_char *ctrl)
{
#ifndef PAR_IO_DIRECT
	u_int mode;
	int ret;
	mode = dbp.mode | IEEE1284_ADDR;
	if(ioctl(dbp.fd, PPNEGOT, &mode))
		return(-1);
	if(wr)
		ret = write(dbp.fd, ctrl, 1);
	else
		ret = read(dbp.fd, ctrl, 1);
	mode &= ~IEEE1284_ADDR;
	if(ioctl(dbp.fd, PPNEGOT, &mode))
		return(-1);
	return(ret);
#else
	if (wr)
		outb(*ctrl, epp_addr_port);
	else 
		*ctrl = inb(epp_addr_port);
	return 1;
#endif
}

/*
 * set write pointer;
 * within the 2kByte fpga buffer;
 * aligned to 32 byte blocks;
 * addr is byte address;
 * returns ioctl() error code, 0=no error;
 * errno is set to indicate the error;
 */
int
dbp_set_wptr(int addr)
{
	u_char data;

	data = 0x80 | ((addr >> 5) & 0x3f);
	return(dbp_ctrl(1, &data));
}

/*
 * set read pointer;
 * within the 2kByte fpga buffer;
 * aligned to 32 byte blocks;
 * addr is byte address;
 * returns ioctl() error code, 0=no error;
 * errno is set to indicate the error;
 */
int
dbp_set_rptr(int addr)
{
	u_char data;

	data = 0xc0 | ((addr >> 5) & 0x3f);
	return(dbp_ctrl(1, &data));
}

/*
 * write a block of data;
 * data is written to position of write pointer;
 * pointer auto-increments;
 * use dbp_set_wptr() to set the pointer;
 * returns write() return code;
 */
int
dbp_write_data(const u_char *buf, int n)
{
#ifndef PAR_IO_DIRECT
	return(write(dbp.fd, buf, n));
#else
	int i;

	for (i=0; i<n; i++)
		outb(buf[i], epp_data_port);
	return  n;
#endif
}

/*
 * read a block of data;
 * data is read from position of the read pointer;
 * pointer auto-increments;
 * use dbp_set_rptr() to set read pointer;
 * returns read() return code;
 */
int
dbp_read_data(u_char *buf, int n)
{
#ifndef PAR_IO_DIRECT
	return(read(dbp.fd, buf, n));
#else
	int i;
	for (i=0; i<n; i++)
		buf[i] = inb(epp_data_port);
	return n;
#endif
}

/*
 * set debug protocol;
 */
int
dbp_set_protocol(dbp_Protocol protocol)
{
	/*
	 * parallel port must be open;
	 */
    if(dbp.fd < 0) {
        fprintf(stderr,"dbp_set_protocol: device not open\n");
        return -1;
    }
	/*
	 * always configure the fpga;
	 * this will also bring the port in the default for EPP mode;
	 */
#ifdef	EPP_JTAG
   	if((dbp.epp && protocol == dbp_JTAG) || protocol != dbp_JTAG) {
#else
   	if(protocol != dbp_JTAG) {
#endif
		dbp_cr(1);
		dbp_config_fpga();
		dbp.mode = IEEE1284_MODE_EPP;
		dbp.mode_str = "IEEE1284_MODE_EPP";
#ifndef PAR_IO_DIRECT
		if(ioctl(dbp.fd, PPSETMODE, &dbp.mode)) {
			perror("dbp_set_protocol: PPSETMODE IEEE1284_MODE_EPP\n");
			return(-1);
		}
		dbp_cr(0);
#endif
	}
	dbp.protocol = protocol;
	dbp.protocol_str = protocol_str[dbp.protocol];
	if(protocol == dbp_JTAG)
		set_jtag_transport();
    return 0;
}

int
dbp_jtag_write(transport_specific_param *p, int x)
{
    /* wiggle pp bits to set tdi, tms, tck (trst not avaiable)
    *  Debug board must be in jtag mode aready
    */

    const int PP_TDI = 1<<2;
    const int PP_TMS = 1<<1;
    const int PP_TCK = 1<<0;
    u8 data = ((x&TDI)?PP_TDI:0) | ((x&TMS)?PP_TMS:0) | ((x&TCK)?PP_TCK:0);
    dbp_state *pp = (dbp_state*)p;

    /* if could use epp
     *     if(write(pp->fd, &tck_tms_tdi_trst, 1)==1)
     *         return 0;
     *     else
     *         return -1;
     */
    if (pp->protocol == dbp_SIM) return sim_jtag_write(pp->fd, x); 
    else if (pp->protocol == dbp_MUX) {
	unsigned char data = x;
	data |= 0x80;
	write(pp->fd, &data, 1);
	return 0;
    }
#ifdef	EPP_JTAG
  #ifndef PAR_IO_DIRECT
    if (pp->epp) {
	data |= 0x20;
	if(dbp_ctrl(1, &data) == 1)
		return(0);
	else
		return(-1);
    } else {
	if(ioctl (pp->fd, PPWDATA, &data)) {
	    perror (" PPWDATA in dbp_jtag_write");
	    return -1;
	} else {
	    return 0;
	}
    }
  #else
    if (pp->epp) {
	data |= 0x20;
        outb(data, epp_addr_port); 
    } else 
        outb(data, spp_data_port);
        
    return 0;
  #endif
#else
  #ifndef PAR_IO_DIRECT
    if(ioctl (pp->fd, PPWDATA, &data)) {
        perror (" PPWDATA in dbp_jtag_write");
        return -1;
    } else {
        return 0;
    }
  #else
    outb(data, spp_data_port); 
    return 0;
  #endif
#endif
}

int
dbp_jtag_read(transport_specific_param *p)
{
    /* read pp status and return state of busy bit
    *  Debug board must be in jtag mode aready
    */

    unsigned char status;
    unsigned char mask = PARPORT_STATUS_PAPEROUT;
    unsigned char val  = PARPORT_STATUS_PAPEROUT;

    dbp_state *pp = (dbp_state*)p;	 
    if (pp->protocol == dbp_SIM) 
	return sim_jtag_read(pp->fd) & TDO; 
    else if (pp->protocol == dbp_MUX) {
	unsigned char data = 0;
	write(pp->fd, &data, 1);
	read(pp->fd, &data, 1);
	return data & TDO;
    }

#ifndef PAR_IO_DIRECT
    if(ioctl (pp->fd, PPRSTATUS, &status)) {
        perror (" PPRSTATUS in dbp_jtag_read");
        return -1;
    }
#else 
    status = inb(spp_sts_port);
#endif

    if ((status & mask) == val)
        return 1;
    else
        return 0;
}

int
dbp_jtag_wait(transport_specific_param *p, int cycle)
{
    /*
    *    struct timespec ts;
    *
    *    ts.tv_sec = 0;
    *    ts.tv_nsec = 1000;
    *    nanosleep (&ts, NULL);
    */

    /* No need for a wait since we provide the clocking */

    dbp_state *pp = (dbp_state*)p;
    if (pp->protocol == dbp_SIM) return sim_jtag_stall(pp->fd, cycle); 

    return 0;
}

static int
set_jtag_transport()
{
    static jtag_TransportInfo  jtag;

    jtag.write = dbp_jtag_write;
    jtag.read  = dbp_jtag_read;
    jtag.wait  = dbp_jtag_wait;
    jtag.p     = &dbp;

    return jtag_set_transport(&jtag);
}