rdp_vms.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: rdp_vms.v,v 1.1.1.1 2002/05/02 03:28:46 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: rdp
// description: RDP top level with only the memspan and a memspan test driver
//
// designer: Phil Gossett, hacked by Scott
// date: 11/2/94
//
////////////////////////////////////////////////////////////////////////
module rdp (clk, gclk, reset_l, iddq,
cbus_read_enable, cbus_write_enable,
cbus_select, cbus_command,
xbus_cs_data, xbus_cs_valid, vm_in, vm_dv,
flush, freeze, unfreeze,
grant, start, finish, read_grant,
dma_write_enable, dma_read_enable,
cs_xbus_req, vm_out, stopgclock,
rdramreq, read_request,
cmd_busy, pipe_busy, tmem_busy,
cbus_data, dbus_data, ebus_data);
input clk;
input gclk;
input reset_l;
input iddq; // true to power down tmem
input cbus_read_enable; // to ms
input cbus_write_enable; // to ms
input [1:0] cbus_select; // to ms
input [2:0] cbus_command; // to ms
input [63:0] xbus_cs_data;
input xbus_cs_valid;
input [7:0] vm_in; // color index pixels from video memory
input vm_dv; // vm pixel data valid
input flush; // CP0 control bit to EW
input freeze; // CP0 control bit to MS
input unfreeze; // strobe due to rdp cmd DMA reg being written
input grant; //dma grant
input start; //dma data valid
input finish; //dma read last cycle
input read_grant; // to be added to ms
input dma_write_enable; //tristate dma data out enable
input dma_read_enable; //tristate dma data in enable
output cs_xbus_req;
output [15:0] vm_out; // pixel bus to vm
output stopgclock; //stall output
output rdramreq; //dma request
output read_request; //request cbus read
output cmd_busy; // from cs state
output pipe_busy; // from ms state
output tmem_busy; // from tc state
inout [31:0] cbus_data;
inout [63:0] dbus_data;
inout [7:0] ebus_data;
// Add all the wires here ie pipe interface to MS