//`define DEBUG

task cbus_write;
  input	[CBUS_DATA_SIZE-1:0] address;
  input	[CBUS_DATA_SIZE-1:0] data;
  begin
    while (!dma_ready)
	@(posedge clock);
    cbus_command <= CBUS_WRITE_COMMAND;
    cbus_data_reg <= address;
    @(posedge clock);

    cbus_command <= CBUS_IDLE_COMMAND;
    cbus_data_reg <= data;
    @(posedge clock);
  end
endtask

task cbus_refresh;
  begin
    while (!dma_ready)
	@(posedge clock);
    cbus_command <= CBUS_REFRESH_COMMAND;
    cbus_data_reg <= 'hxxxxxxxx;
    @(posedge clock);

    cbus_command <= CBUS_IDLE_COMMAND;
    @(posedge clock);
  end
endtask

task cbus_dma_write;
  input masked;
  input down;
  input	[CBUS_DATA_SIZE-1:0] address;
  input	[DMA_DEVICE_SIZE-1:0] device;
  input [31:0] delay;
  input	[31:0] length;

  reg	[DMA_DELAY_SIZE-1:0] start_delay;
  reg	[DMA_LENGTH_SIZE-1:0] byte_length;
  reg	nseq;

  begin
    start_delay = delay;
    byte_length = length - 1;

    while (!dma_ready)
	@(posedge clock);

`ifdef DEBUG
    $write("dma write ");
    if (masked)
      $write("masked ");
    if (down)
      $write("down ");
    else
      $write("up ");
    $write("to 0x%x, length 0%x at time %d\n", address, length, $time);
`endif

    cbus_command <= CBUS_DMA_COMMAND;
    cbus_data_reg <= address;

    @(posedge clock);

    nseq = (masked || down);
    cbus_command <= CBUS_IDLE_COMMAND;
    cbus_data_reg <= {1'b0, masked, down, nseq, device, start_delay,
		      1'b0, byte_length};
    @(posedge clock);
  end
endtask

task cbus_dma_read;
  input subblock;
  input down;
  input	[CBUS_DATA_SIZE-1:0] address;
  input	[DMA_DEVICE_SIZE-1:0] device;
  input	[31:0] delay;
  input	[31:0] length;

  reg	[DMA_DELAY_SIZE-1:0] start_delay;
  reg	[DMA_LENGTH_SIZE-1:0] byte_length;
  reg	nseq;

  begin
    start_delay = delay;
    byte_length = length - 1;

    while (!dma_ready)
      @(posedge clock);

`ifdef DEBUG
    $write("dma read ");
    if (subblock)
      $write("subblock ");
    if (down)
      $write("down ");
    else
      $write("up ");
    $write("from 0x%x, length 0%x at time %d\n", address, length, $time);
`endif

    cbus_command <= CBUS_DMA_COMMAND;
    cbus_data_reg <= address;
    @(posedge clock);

    nseq = (subblock || down);
    cbus_command <= CBUS_IDLE_COMMAND;
    cbus_data_reg <= {subblock, 1'b0, down, nseq, device, start_delay,
		      1'b1, byte_length};
    @(posedge clock);
  end
endtask

task dbus_put_data;
  input	[DBUS_DATA_SIZE-1:0] dbus_data_val;
  input	[EBUS_DATA_SIZE-1:0] ebus_data_val;
  input	[31:0] delay;
  begin
     while (!dma_start)
	@(posedge clock);
    repeat(-(2+delay))
	@(posedge clock);
    dbus_data_out <= dbus_data_val;
    ebus_data_out <= ebus_data_val;
    @(posedge clock);
  end
endtask

task dbus_get_data;
  output	[DBUS_DATA_SIZE-1:0] dbus_data_val;
  output	[EBUS_DATA_SIZE-1:0] ebus_data_val;
  input	[31:0] delay;
  integer i;
  begin
    while (!dma_start)
      @(posedge clock);

    repeat(3-delay)
      @(posedge clock);
    dbus_data_val = dbus_data_reg;
    ebus_data_val = ebus_data_reg;
  end
endtask

task initialize_dram;
  begin

    // set reset mode
    cbus_write(BUS_ADDRESS_RI_MODE, {LOW, LOW, RDRAM_RESET_MODE});

    // write the RI current control register
    cbus_write(BUS_ADDRESS_RI_CONFIG, 'b0_001000);

    // wait for the current register to propogate
    repeat (32) @(posedge clock);

    // load current control register
    cbus_write(BUS_ADDRESS_RI_CURRENT_LOAD, 0);

    // set RAC transmit and receive selects
    cbus_write(BUS_ADDRESS_RI_SELECT, {4'b0001, 4'b0100});

    // wait for reset_l to take hold
    repeat (80) @(posedge clock);

    // set standby mode
    cbus_write(BUS_ADDRESS_RI_MODE, {HIGH, HIGH, RDRAM_STANDBY_MODE});

    // Initialize the RDRAM delay register
    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_DELAY | RDRAM_GLOBAL_CONFIG,
		   BUS_DEVICE_MI, -2, 16);
    dbus_put_data({2{'h18_08_28_38}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_RAS_INTERVAL | RDRAM_GLOBAL_CONFIG,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{8'd1, 8'd7, 8'd10, 8'd4}}, 8'hxx, -2);

    // configure RDRAM 3

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_DEVICE_ID,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{RDRAM_3_DEVICE_ID, 3'b0, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_MODE + RDRAM_3_CONFIG,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{8'b0000_0010, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);
    repeat (10) @(posedge clock);

    // configure RDRAM 2

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_DEVICE_ID,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{RDRAM_2_DEVICE_ID, 3'b0, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_MODE + RDRAM_2_CONFIG,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{8'b0000_0010, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);
    repeat (10) @(posedge clock);

    // configure RDRAM 1

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_DEVICE_ID,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{RDRAM_1_DEVICE_ID, 3'b0, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_MODE + RDRAM_1_CONFIG,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{8'b0000_0010, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);
    repeat (10) @(posedge clock);

    // configure RDRAM 0

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_DEVICE_ID,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{RDRAM_0_DEVICE_ID, 3'b0, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    cbus_dma_write(`DMA_UNMASKED, `DMA_UP,
		   BUS_ADDRESS_RDRAM_MODE + RDRAM_0_CONFIG,
		   BUS_DEVICE_MI, -2, 8);
    dbus_put_data({2{8'b0000_0010, 8'b0, 8'b0, 8'b0}}, 8'hxx, -2);

    repeat (10) @(posedge clock);

    // validate the banks before refreshing begins

    cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, BUS_ADDRESS_DRAM + 'h00_0000,
		  BUS_DEVICE_MI, 3, 8);
    while (!dma_start)
      @(posedge clock);

    cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, BUS_ADDRESS_DRAM + 'h10_0000,
		  BUS_DEVICE_MI, 3, 8);
    while (!dma_start)
      @(posedge clock);

    cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, BUS_ADDRESS_DRAM + 'h20_0000,
		  BUS_DEVICE_MI, 3, 8);
    while (!dma_start)
      @(posedge clock);

    cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, BUS_ADDRESS_DRAM + 'h30_0000,
		  BUS_DEVICE_MI, 3, 8);
    while (!dma_start)
      @(posedge clock);

    // enable refresh
    cbus_write(BUS_ADDRESS_RI_REFRESH, 'b1_1_0_00110100_00110010);

    // wait for the post-write-reg delay
    repeat (10) @(posedge clock);
  end
endtask

task check_data;
  input		[7*8:1] test_name;
  input		[DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
  input		[EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;

  begin
    if (expected_d_data !== actual_d_data)
    begin
      $write("%s: dbus_data_reg expected: 0x%x was: 0x%x at time %d\n",
	     test_name, expected_d_data, actual_d_data, $time);
      errors = errors + 1;
    end
    if (expected_e_data !== actual_e_data)
    begin
      $write("%s: ebus_data_reg expected: 0x%x was: 0x%x at time %d\n",
	     test_name, expected_e_data, actual_e_data, $time);
      errors = errors + 1;
    end
  end
endtask

task check_unmasked;
  input		[7*8:1] test_name;
  integer	i, j;
  begin
    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      while (!dma_start)
	@(posedge clock);

      for (j = 0; j < (i-1); j = j + 1)
      begin
	if ((j != 0) && dma_start)
	begin
	  $write("%s: dma_start expected: %d was %d at time %d\n",
		  test_name, 1'b1, dma_start, $time);
	  errors = errors + 1;
        end
	@(posedge clock);
      end

      if (!dma_last)
      begin
	$write("%s: dma_last expected: %d was %d at time %d\n",
		test_name, 1'b1, dma_last, $time);
	errors = errors + 1;
      end
      @(posedge clock);
    end
  end
endtask

task check_nosubblock;
  input		[7*8:1] test_name;
  integer	i, j;
  begin
    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      while (!dma_start)
	@(posedge clock);

      for (j = 0; j < (i-1); j = j + 1)
      begin
	if ((j != 0) && dma_start)
	begin
	  $write("%s: dma_start expected: %d was %d at time %d\n",
		  test_name, 1'b1, dma_start, $time);
	  errors = errors + 1;
        end
	@(posedge clock);
      end

      if (!dma_last)
      begin
	$write("%s: dma_last expected: %d was %d at time %d\n",
		test_name, 1'b1, dma_last, $time);
	errors = errors + 1;
      end
      @(posedge clock);
    end
  end
endtask

task check_masked;
  input		[7*8:1] test_name;
  integer	i, j;
  begin
    for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
    begin
      while (!dma_start)
	@(posedge clock);

      for (j = 0; j < (i-1); j = j + 1)
      begin
	if ((j != 0) && dma_start)
	begin
	  $write("%s: dma_start expected: %d was %d at time %d\n",
		  test_name, 1'b1, dma_start, $time);
	  errors = errors + 1;
        end
	@(posedge clock);
      end

      if (!dma_last)
      begin
	$write("%s: dma_last expected: %d was %d at time %d\n",
	       test_name, 1'b1, dma_last, $time);
	errors = errors + 1;
      end
      @(posedge clock);
    end
  end
endtask

task check_subblock;
  input		[7*8:1] test_name;
  integer	i, j;
  begin
    for (i = 0; i < 2; i = i + 1)
    begin
      while (!dma_start)
	@(posedge clock);

      for (j = 0; j < (2-1); j = j + 1)
      begin
	if ((j != 0) && dma_start)
	begin
	  $write("%s: dma_start expected: %d was %d at time %d\n",
		  test_name, 1'b1, dma_start, $time);
	  errors = errors + 1;
        end
	@(posedge clock);
      end

      if (!dma_last)
      begin
	$write("%s: dma_last expected: %d was %d at time %d\n",
	       test_name, 1'b1, dma_last, $time);
	errors = errors + 1;
      end
      @(posedge clock);
    end

    for (i = 0; i < 4; i = i + 1)
    begin
      while (!dma_start)
      begin
	@(posedge clock);
      end

      for (j = 0; j < (4-1); j = j + 1)
      begin
	if ((j != 0) && dma_start)
	begin
	  $write("%s: dma_start expected: %d was %d at time %d\n",
		  test_name, 1'b1, dma_start, $time);
	  errors = errors + 1;
        end
	@(posedge clock);
      end

      if (!dma_last)
      begin
	$write("%s: dma_last expected: %d was %d at time %d\n",
	       test_name, 1'b1, dma_last, $time);
	errors = errors + 1;
      end
      @(posedge clock);
    end
  end
endtask

task check_single;
  input		[7*8:1] test_name;
  integer	i, j;

  begin
    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      for (j = 0; j < i; j = j + 1)
      begin
	while (!dma_start)
	  @(posedge clock);
	if (!dma_last)
	begin
	  $write("%s: dma_last expected: %d was %d at time %d\n",
		 test_name, 1'b1, dma_last, $time);
	  errors = errors + 1;
	end
	@(posedge clock);
      end
    end
  end
endtask

task check_refresh;
  input		[7*8:1] test_name;
  integer	got_refresh;
  begin
    got_refresh = 0;

    while (!dma_start)
    begin
      if (c_ctl_ld)
	got_refresh = 1;
      @(posedge clock);
    end
    if (!got_refresh)
    begin
      $write("%s: c_ctl_ld did not go high after refresh (around time %d)\n",
	     test_name, $time);
      errors = errors + 1;
    end
  end
endtask