test001.v
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//
// test001 Vary start_delay values on dma write operation
//
`define LO_DELAY -5
`define HI_DELAY 0
task test001;
fork
test001_check;
test001_cmddata;
join
endtask
task test001_check;
integer i;
begin
for (i = 0; i < 12; i = i + 1)
begin
while (!dma_start)
@(posedge clock);
if (!dma_last)
begin
$write("test001: dma_last expected: %d was %d at time %d\n",
1'b1, dma_last, $time);
errors = errors + 1;
end
@(posedge clock);
end
end
endtask
task test001_cmddata;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
reg [EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;
reg [DMA_DELAY_SIZE-1:0] start_delay;
integer i;
begin
// For values up to -2, delay putting data on buses until dma_start
address = 0;
for (i = `LO_DELAY; i <= -2; i = i + 1)
begin
start_delay = i;
expected_d_data = {8{start_delay}};
expected_e_data = start_delay;
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address, BUS_DEVICE_MI, i, 8);
dbus_put_data(expected_d_data, expected_e_data, i);
address = address + 8;
end
// For remaining values, have the data on the buses ahead of time
for (i = -1; i <= `HI_DELAY; i = i + 1)
begin
start_delay = i;
expected_d_data = {8{start_delay}};
expected_e_data = start_delay;
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address, BUS_DEVICE_MI, i, 8);
dbus_data_out <= expected_d_data;
ebus_data_out <= expected_e_data;
while (!dma_start)
@(posedge clock);
address = address + 8;
end
address = 0;
for (i = `LO_DELAY; i <= `HI_DELAY; i = i + 1)
begin
start_delay = i;
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 8);
dbus_get_data(actual_d_data, actual_e_data, 3);
expected_d_data = {8{start_delay}};
expected_e_data = start_delay;
check_data("test001", expected_d_data, actual_d_data,
expected_e_data, actual_e_data);
address = address + 8;
end
end
endtask