test008.v
1.33 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
//
// test008 Test of masked DMA write commands
//
task test008;
fork
test008_check;
test008_cmddata;
join
endtask
task test008_check;
begin
check_masked("test008");
end
endtask
task test008_cmddata;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
reg [EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;
integer i, j;
begin
address = 0;
for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
begin
cbus_dma_write(`DMA_MASKED, `DMA_UP, address, BUS_DEVICE_MI, -2, i*8);
while (!dma_start)
@(posedge clock);
dbus_data_out <= 64'hffffffff_ffffffff;
ebus_data_out <= 8'hff;
@(posedge clock);
for (j = 0; j < i; j = j + 1)
begin
dbus_data_out <= {2{address}};
ebus_data_out <= address[10:3];
@(posedge clock);
address = address + 8;
end
end
address = 0;
for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
begin
for (j = 0; j < i; j = j + 1)
begin
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 8);
dbus_get_data(actual_d_data, actual_e_data, 3);
expected_d_data = {2{address}};
expected_e_data = address[10:3];
check_data("test008", expected_d_data, actual_d_data,
expected_e_data, actual_e_data);
address = address + 8;
end
end
end
endtask