rsp_capture.v
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reg [31:0] fpC_rsp;
wire cbus_write_enable = `rsp_path.sp_cbus_write_enable ||
`rsp_path.mem_cbus_write_enable ||
`rsp_path.cmd_cbus_write_enable;
reg [31:0] cbus_data_reg;
reg [63:0] dbus_data_reg;
integer idx;
reg [15:0] df_wen_v, ls_data_v, su_bwe_ac_d1;
always @(posedge `CLK) su_bwe_ac_d1 <= `vu_path.su_bwe_ac;
wire ctc2 = `vu_path.su_wrcmpcd_wb ||
`vu_path.su_wrcryout_wb ||
`vu_path.su_wrcmpcdad_wb;
always @(negedge `CLK)
begin
cbus_data_reg = `rsp_path.cbus_data;
dbus_data_reg = `rsp_path.dbus_data;
if (!cbus_write_enable)
for (idx=0; idx<32; idx=idx+1)
if (cbus_data_reg[idx]===1'bx || cbus_data_reg[idx]===1'bz)
cbus_data_reg[idx] = 1'b0;
if (!`rsp_path.sp_dbus_write_enable)
for (idx=0; idx<64; idx=idx+1)
if (dbus_data_reg[idx]===1'bx || dbus_data_reg[idx]===1'bz)
dbus_data_reg[idx] = 1'b0;
df_wen_v = ~`rsp_path.dmemx2.df_wen_l;
ls_data_v[15] = `rsp_path.su.sudp.suloaden || su_bwe_ac_d1[15] || ctc2;
ls_data_v[14] = `rsp_path.su.sudp.suloaden || su_bwe_ac_d1[14] || ctc2;
ls_data_v[13:0] = su_bwe_ac_d1[13:0];
end
initial
begin
if ($test$plusargs("qsim_capture_rsp"))
begin
fpC_rsp = $fopen("capture_rsp.tab");
$fwrite(fpC_rsp,
"clk @C 1(10) 0(10)\n",
"reset_l @I @E 2 \n",
"iddq_test @I @E 2 \n",
"frozen @I @E 2 \n",
"sp_cbus_read_enable @I @E 2 \n",
"sp_cbus_write_enable @I @E 2 \n",
"mem_cbus_write_enable @I @E 2 \n",
"cmd_cbus_read_enable @I @E 2 \n",
"cmd_cbus_write_enable @I @E 2 \n",
"cbus_select[1:0] @I @E 2 \n",
"cbus_command[2:0] @I @E 2 \n",
"dma_start @I @E 2 \n",
"dma_last @I @E 2 \n",
"sp_dma_grant @I @E 2 \n",
"sp_read_grant @I @E 2 \n",
"cmd_dma_grant @I @E 2 \n",
"cmd_read_grant @I @E 2 \n",
"sp_dbus_read_enable @I @E 2 \n",
"sp_dbus_write_enable @I @E 2 \n",
"cbuf_ready @I @E 2 \n",
"cmd_busy @I @E 2 \n",
"pipe_busy @I @E 2 \n",
"tmem_busy @I @E 2 \n",
"cbus_data[31:0] @B cbus_write_enable 1 @E 5 @S 15 \n",
"dbus_data[63:0] @B sp_dbus_write_enable 1 @E 5 @S 15 \n",
"cbus_write_enable @I @E 0 \n",
"dbus_write_enable @I @E 0 \n",
"sp_dma_request @O @S 15 \n",
"sp_read_request @O @S 15 \n",
"mem_read_request @O @S 15 \n",
"cmd_dma_request @O @S 15 \n",
"cmd_read_request @O @S 15 \n",
"cbuf_write @O @S 15 \n",
"flush @O @S 15 \n",
"freeze @O @S 15 \n",
"unfreeze @O @S 15 \n",
"sp_interrupt @O @S 15 \n",
"xbus_data[63:0] @O @S 15 \n",
//VU interface probe
"su_instvld_rd @O @S 15 \n",
"su_storeinst_rd @O @S 15 \n",
"su_vseqone_rd @O @S 15 \n",
"su_instelem_rd[3:0] @O @S 15 \n",
"su_instfunc_rd[5:0] @O @S 15 \n",
"su_rdcmpcd_rd @O @S 15 \n",
"su_rdcryout_rd @O @S 15 \n",
"su_rdcmpcdad_rd @O @S 15 \n",
"su_wrcmpcd_wb @O @S 15 \n",
"su_wrcryout_wb @O @S 15 \n",
"su_wrcmpcdad_wb @O @S 15 \n",
"su_st_rnum_rd[4:0] @O @S 15 \n",
"su_xp_rnum_rd[4:0] @O @S 15 \n",
"su_ld_rnum_ac[4:0] @O @S 15 \n",
"su_vs_addr_rd[4:0] @O @S 15 \n",
"su_vt_addr_rd[4:0] @O @S 15 \n",
"su_vd_addr_ac[4:0] @O @S 15 \n",
"su_wbv_wr_en_ac @O @S 15 \n",
"su_bwe_ac[15:0] @O @S 15 \n",
"su_xposeop_rdac @O @S 15 \n",
"ls_data_15[7:0] @O @V ls_data_v_0 @S 15 \n",
"ls_data_14[7:0] @O @V ls_data_v_1 @S 15 \n",
"ls_data_13[7:0] @O @V ls_data_v_2 @S 15 \n",
"ls_data_12[7:0] @O @V ls_data_v_3 @S 15 \n",
"ls_data_11[7:0] @O @V ls_data_v_4 @S 15 \n",
"ls_data_10[7:0] @O @V ls_data_v_5 @S 15 \n",
"ls_data_09[7:0] @O @V ls_data_v_6 @S 15 \n",
"ls_data_08[7:0] @O @V ls_data_v_7 @S 15 \n",
"ls_data_07[7:0] @O @V ls_data_v_8 @S 15 \n",
"ls_data_06[7:0] @O @V ls_data_v_9 @S 15 \n",
"ls_data_05[7:0] @O @V ls_data_v_10 @S 15 \n",
"ls_data_04[7:0] @O @V ls_data_v_11 @S 15 \n",
"ls_data_03[7:0] @O @V ls_data_v_12 @S 15 \n",
"ls_data_02[7:0] @O @V ls_data_v_13 @S 15 \n",
"ls_data_01[7:0] @O @V ls_data_v_14 @S 15 \n",
"ls_data_00[7:0] @O @V ls_data_v_15 @S 15 \n",
"ls_data_v_0 @V \n",
"ls_data_v_1 @V \n",
"ls_data_v_2 @V \n",
"ls_data_v_3 @V \n",
"ls_data_v_4 @V \n",
"ls_data_v_5 @V \n",
"ls_data_v_6 @V \n",
"ls_data_v_7 @V \n",
"ls_data_v_8 @V \n",
"ls_data_v_9 @V \n",
"ls_data_v_10 @V \n",
"ls_data_v_11 @V \n",
"ls_data_v_12 @V \n",
"ls_data_v_13 @V \n",
"ls_data_v_14 @V \n",
"ls_data_v_15 @V \n",
//DMEM interface probe
"df_wen_l[15:0] @O @S 15 \n",
"df_addr_low[7:0] @O @S 15 \n",
"df_addr_high[7:0] @O @S 15 \n",
"df_datain_15[7:0] @O @V df_wen_v_0 @S 15 \n",
"df_datain_14[7:0] @O @V df_wen_v_1 @S 15 \n",
"df_datain_13[7:0] @O @V df_wen_v_2 @S 15 \n",
"df_datain_12[7:0] @O @V df_wen_v_3 @S 15 \n",
"df_datain_11[7:0] @O @V df_wen_v_4 @S 15 \n",
"df_datain_10[7:0] @O @V df_wen_v_5 @S 15 \n",
"df_datain_09[7:0] @O @V df_wen_v_6 @S 15 \n",
"df_datain_08[7:0] @O @V df_wen_v_7 @S 15 \n",
"df_datain_07[7:0] @O @V df_wen_v_8 @S 15 \n",
"df_datain_06[7:0] @O @V df_wen_v_9 @S 15 \n",
"df_datain_05[7:0] @O @V df_wen_v_10 @S 15 \n",
"df_datain_04[7:0] @O @V df_wen_v_11 @S 15 \n",
"df_datain_03[7:0] @O @V df_wen_v_12 @S 15 \n",
"df_datain_02[7:0] @O @V df_wen_v_13 @S 15 \n",
"df_datain_01[7:0] @O @V df_wen_v_14 @S 15 \n",
"df_datain_00[7:0] @O @V df_wen_v_15 @S 15 \n",
"df_wen_v_0 @V \n",
"df_wen_v_1 @V \n",
"df_wen_v_2 @V \n",
"df_wen_v_3 @V \n",
"df_wen_v_4 @V \n",
"df_wen_v_5 @V \n",
"df_wen_v_6 @V \n",
"df_wen_v_7 @V \n",
"df_wen_v_8 @V \n",
"df_wen_v_9 @V \n",
"df_wen_v_10 @V \n",
"df_wen_v_11 @V \n",
"df_wen_v_12 @V \n",
"df_wen_v_13 @V \n",
"df_wen_v_14 @V \n",
"df_wen_v_15 @V \n",
"dmem_dataout_15[7:0] @O @S 15 \n",
"dmem_dataout_14[7:0] @O @S 15 \n",
"dmem_dataout_13[7:0] @O @S 15 \n",
"dmem_dataout_12[7:0] @O @S 15 \n",
"dmem_dataout_11[7:0] @O @S 15 \n",
"dmem_dataout_10[7:0] @O @S 15 \n",
"dmem_dataout_09[7:0] @O @S 15 \n",
"dmem_dataout_08[7:0] @O @S 15 \n",
"dmem_dataout_07[7:0] @O @S 15 \n",
"dmem_dataout_06[7:0] @O @S 15 \n",
"dmem_dataout_05[7:0] @O @S 15 \n",
"dmem_dataout_04[7:0] @O @S 15 \n",
"dmem_dataout_03[7:0] @O @S 15 \n",
"dmem_dataout_02[7:0] @O @S 15 \n",
"dmem_dataout_01[7:0] @O @S 15 \n",
"dmem_dataout_00[7:0] @O @S 15 \n",
//IMEM interface probe
"imem_web @O @S 15 \n",
"imem_datain[63:0] @O @S 15 \n",
"final_pc[8:0] @O @S 15 \n",
"rd_inst[63:0] @O @S 15 \n",
// Misc
"dma_busy @O @S 15 \n",
"halt @O @S 15 \n",
"set_broke @O @S 15 \n"
);
$fdisplay(fpC_rsp);
@(posedge `CLK);
forever
begin
@(negedge `CLK);
#4;
$fwrite(fpC_rsp,
"%b ", `rsp_path.reset_l,
"%b ", `rsp_path.iddq_test,
"%b ", `rsp_path.frozen,
"%b ", `rsp_path.sp_cbus_read_enable,
"%b ", `rsp_path.sp_cbus_write_enable,
"%b ", `rsp_path.mem_cbus_write_enable,
"%b ", `rsp_path.cmd_cbus_read_enable,
"%b ", `rsp_path.cmd_cbus_write_enable,
"0x%h ", `rsp_path.cbus_select[1:0],
"0x%h ", `rsp_path.cbus_command[2:0],
"%b ", `rsp_path.dma_start,
"%b ", `rsp_path.dma_last,
"%b ", `rsp_path.sp_dma_grant,
"%b ", `rsp_path.sp_read_grant,
"%b ", `rsp_path.cmd_dma_grant,
"%b ", `rsp_path.cmd_read_grant,
"%b ", `rsp_path.sp_dbus_read_enable,
"%b ", `rsp_path.sp_dbus_write_enable,
"%b ", `rsp_path.cbuf_ready,
"%b ", `rsp_path.cmd_busy,
"%b ", `rsp_path.pipe_busy,
"%b ", `rsp_path.tmem_busy,
"0x%h ", cbus_data_reg,
"0x%h ", dbus_data_reg,
"%b ", cbus_write_enable,
"%b ", `rsp_path.sp_dbus_write_enable,
"%b ", `rsp_path.sp_dma_request,
"%b ", `rsp_path.sp_read_request,
"%b ", `rsp_path.mem_read_request,
"%b ", `rsp_path.cmd_dma_request,
"%b ", `rsp_path.cmd_read_request,
"%b ", `rsp_path.cbuf_write,
"%b ", `rsp_path.flush,
"%b ", `rsp_path.freeze,
"%b ", `rsp_path.unfreeze,
"%b ", `rsp_path.sp_interrupt,
"0x%h ", `rsp_path.xbus_data[63:0],
"%b ", `vu_path.su_instvld_rd,
"%b ", `vu_path.su_storeinst_rd,
"%b ", `vu_path.su_vseqone_rd,
"0x%h ", `vu_path.su_instelem_rd[3:0],
"0x%h ", `vu_path.su_instfunc_rd[5:0],
"%b ", `vu_path.su_rdcmpcd_rd,
"%b ", `vu_path.su_rdcryout_rd,
"%b ", `vu_path.su_rdcmpcdad_rd,
"%b ", `vu_path.su_wrcmpcd_wb,
"%b ", `vu_path.su_wrcryout_wb,
"%b ", `vu_path.su_wrcmpcdad_wb,
"0x%h ", `vu_path.su_st_rnum_rd[4:0],
"0x%h ", `vu_path.su_xp_rnum_rd[4:0],
"0x%h ", `vu_path.su_ld_rnum_ac[4:0],
"0x%h ", `vu_path.su_vs_addr_rd[4:0],
"0x%h ", `vu_path.su_vt_addr_rd[4:0],
"0x%h ", `vu_path.su_vd_addr_ac[4:0],
"%b ", `vu_path.su_wbv_wr_en_ac,
"0x%h ", `vu_path.su_bwe_ac[15:0],
"%b ", `vu_path.su_xposeop_rdac,
"0x%h ", `rsp_path.ls_data[7:0],
"0x%h ", `rsp_path.ls_data[15:8],
"0x%h ", `rsp_path.ls_data[23:16],
"0x%h ", `rsp_path.ls_data[31:24],
"0x%h ", `rsp_path.ls_data[39:32],
"0x%h ", `rsp_path.ls_data[47:40],
"0x%h ", `rsp_path.ls_data[55:48],
"0x%h ", `rsp_path.ls_data[63:56],
"0x%h ", `rsp_path.ls_data[71:64],
"0x%h ", `rsp_path.ls_data[79:72],
"0x%h ", `rsp_path.ls_data[87:80],
"0x%h ", `rsp_path.ls_data[95:88],
"0x%h ", `rsp_path.ls_data[103:96],
"0x%h ", `rsp_path.ls_data[111:104],
"0x%h ", `rsp_path.ls_data[119:112],
"0x%h ", `rsp_path.ls_data[127:120],
"%b ", ls_data_v[0],
"%b ", ls_data_v[1],
"%b ", ls_data_v[2],
"%b ", ls_data_v[3],
"%b ", ls_data_v[4],
"%b ", ls_data_v[5],
"%b ", ls_data_v[6],
"%b ", ls_data_v[7],
"%b ", ls_data_v[8],
"%b ", ls_data_v[9],
"%b ", ls_data_v[10],
"%b ", ls_data_v[11],
"%b ", ls_data_v[12],
"%b ", ls_data_v[13],
"%b ", ls_data_v[14],
"%b ", ls_data_v[15],
"0x%h ", `rsp_path.dmemx2.df_wen_l,
"0x%h ", `rsp_path.dmemx2.df_addr_low[11:4],
"0x%h ", `rsp_path.dmemx2.df_addr_high[11:4],
"0x%h ", `rsp_path.dmemx2.df_datain[7:0],
"0x%h ", `rsp_path.dmemx2.df_datain[15:8],
"0x%h ", `rsp_path.dmemx2.df_datain[23:16],
"0x%h ", `rsp_path.dmemx2.df_datain[31:24],
"0x%h ", `rsp_path.dmemx2.df_datain[39:32],
"0x%h ", `rsp_path.dmemx2.df_datain[47:40],
"0x%h ", `rsp_path.dmemx2.df_datain[55:48],
"0x%h ", `rsp_path.dmemx2.df_datain[63:56],
"0x%h ", `rsp_path.dmemx2.df_datain[71:64],
"0x%h ", `rsp_path.dmemx2.df_datain[79:72],
"0x%h ", `rsp_path.dmemx2.df_datain[87:80],
"0x%h ", `rsp_path.dmemx2.df_datain[95:88],
"0x%h ", `rsp_path.dmemx2.df_datain[103:96],
"0x%h ", `rsp_path.dmemx2.df_datain[111:104],
"0x%h ", `rsp_path.dmemx2.df_datain[119:112],
"0x%h ", `rsp_path.dmemx2.df_datain[127:120],
"%b ", df_wen_v[0],
"%b ", df_wen_v[1],
"%b ", df_wen_v[2],
"%b ", df_wen_v[3],
"%b ", df_wen_v[4],
"%b ", df_wen_v[5],
"%b ", df_wen_v[6],
"%b ", df_wen_v[7],
"%b ", df_wen_v[8],
"%b ", df_wen_v[9],
"%b ", df_wen_v[10],
"%b ", df_wen_v[11],
"%b ", df_wen_v[12],
"%b ", df_wen_v[13],
"%b ", df_wen_v[14],
"%b ", df_wen_v[15],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[7:0],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[15:8],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[23:16],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[31:24],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[39:32],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[47:40],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[55:48],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[63:56],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[71:64],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[79:72],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[87:80],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[95:88],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[103:96],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[111:104],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[119:112],
"0x%h ", `rsp_path.dmemx2.dmem_dataout[127:120],
//IMEM interface probe
"%b ", `rsp_path.imem.web,
"0x%h ", `rsp_path.imem.di,
"0x%h ", `rsp_path.imem.a,
"0x%h ", `rsp_path.imem.dout,
// Misc
"%b ", `rsp_path.io_mem_dma.dma_busy,
"%b ", `rsp_path.io_mem_dma.halt,
"%b ", `rsp_path.io_mem_dma.set_broke
);
$fdisplay(fpC_rsp);
end
end
end