#
# Copyright (C) 1996-1998 by the Board of Trustees
#    of Leland Stanford Junior University.
# 
# This file is part of the SimOS distribution. 
# See LICENSE file for terms of the license. 
#

########################################################################
#                                                                      #
# Default parameter values for SimOS. This file should be sourced at   #
# the start of your init.simos file and then you can change any of the #
# values below that source. Note that a few of the parameters are only #
# set if you are not restoring a checkpoint. These parameters are      #
# saved in the checkpoint and can not be changed.                      #
#                                                                      #
########################################################################

#
# MACHINES:
#
    if {!$SIMOS(RestoringCpt)} {
    # Number of machines to simulate
        set PARAM(MACHINE.Count)    1
    }

#
# CPU:
#   
#   You can dynamically switch between CPU simulators. The model
#   determines which one you start in.
#
    if {!$SIMOS(RestoringCpt)} {
        # Number of processors to simulate
        set PARAM(CPU.Count)   1
    }

if {$SIMOS(ISA)=="MIPS" || $SIMOS(ISA)=="MIPS32"} { 
    # Which instruction set architecture... currently only MIPS
    set PARAM(CPU.ISA)            "MIPS"
    
    if {$SIMOS(ISA)== "MIPS"} {
        set PARAM(TLB.Org)        R10000
    } else {
        set PARAM(TLB.Org)        R4000 
    }

    # Which cpu simulator to start in. (EMBRA_PAGE, EMBRA_CACHE, MIPSY)
    if {$SIMOS(EmbraPresent)} {
       set PARAM(CPU.Model)          EMBRA_PAGE
    } else {
       set PARAM(CPU.Model)          MIPSY
    }
}

if {$SIMOS(ISA)=="ALPHA"} { 
    set PARAM(CPU.ISA)   "ALPHA"
    set PARAM(CPU.Model) "GAMMA"
    set PARAM(CPU.Delta.TimeQuantum) 1024

    #bogus:
    set PARAM(TLB.Org)            R4000
}

if {$SIMOS(ISA)=="X86"} { 
    set PARAM(CPU.ISA)   "X86"
    set PARAM(CPU.Model) "X86SIM"

    #bogus:
    set PARAM(TLB.Org)            R4000
}
    # Clock speed in MHz. 
    set PARAM(CPU.Clock)          200

  #
  # Mipsy/MXS specifics
  # 
  console "Current ISA is $SIMOS(ISA) \n"
    if {$SIMOS(ISA) == "MIPS" || $SIMOS(ISA)=="MIPS32"} { 
      set PARAM(CPU.Mipsy.MipsySampleCycles)     0xffffffff
      set PARAM(CPU.Mipsy.MXSSampleCycles)       0
    }
  # 
  # Embra specifics  
  #
  if {$SIMOS(EmbraPresent)} { 
    set PARAM(CPU.Embra.MPinUP)               yes
    set PARAM(CPU.EmbraPage.UseETLB)          yes
    set PARAM(CPU.EmbraCache.UseVQC)          yes  
    set PARAM(CPU.Embra.DisableStat)          yes
    set PARAM(CPU.Embra.InlineQC)             yes
    set PARAM(CPU.Embra.TimeQuantum)         1024
    set PARAM(CPU.Embra.MiscCheckInterval)  50000
    set PARAM(CPU.Embra.PeriodAnnInterval)  [expr 32 * 1024 * 1024]
    set PARAM(CPU.Embra.StatInterval)       [expr 32 * 1024 * 1024]
    set PARAM(CPU.Embra.SeparateMMUs)         no
  }

#
# CACHE:
# 
#   We have two types of caches now:
# 
#   None - don't use caches
#
#   2Level - this consists of separate level 1 instruction and data 
#   caches and a unified level 2 cache. Additionally, there is a 
#   configurable write buffer.  
# 
    set PARAM(CACHE.Model)      2Level

  # 
  # 2Level specifics
  #
    # Size (in kilobytes) of the 1st level instruction cache
    set PARAM(CACHE.2Level.ISize)   32
    # Size (in bytes) of a 1st level instruction cache line
    set PARAM(CACHE.2Level.ILine)   64
    # Associativity of 1st level instruction cache
    set PARAM(CACHE.2Level.IAssoc)   2
 
    # icache inclusion
   if { $SIMOS(ISA)=="ALPHA"} { 
      set PARAM(CACHE.2Level.IInclusion) no
    } else {
      set PARAM(CACHE.2Level.IInclusion) yes
    }

    # Size (in kilobytes) of the 1st level data cache
    set PARAM(CACHE.2Level.DSize)   32    
    # Size (in bytes) of a 1st level data cache line
    set PARAM(CACHE.2Level.DLine)   64
    # Associativity of 1st level data cache
    set PARAM(CACHE.2Level.DAssoc)   2

    # Size (in kilobytes) of the 2nd level unified cache
    set PARAM(CACHE.2Level.L2Size)  1024
    # Size (in bytes) of a 2nd level cache line
    set PARAM(CACHE.2Level.L2Line)   128
    # Associativity of 2nd level unified cache
    set PARAM(CACHE.2Level.L2Assoc)     2

    # Time (in nanoseconds) for a 2nd level cache hit
    set PARAM(CACHE.2Level.L2HitTime)        50

    # The write buffer allows non-blocking writes. 0 turns off the buffer.
    set PARAM(CACHE.2Level.WriteBufferSize) 0

    # 
    set PARAM(CACHE.2Level.UpgradesOnUP)    0

    # Time (in *cycles*) before a NAKed memory request is retried
    set PARAM(CACHE.2Level.NAKRetryTime)    1

#
# CONSOLE:
# 
# 
    if {!$SIMOS(RestoringCpt)} {
        # Number of consoles
        set PARAM(CONSOLE.Count)  1
    }
    
    set PARAM(CONSOLE.Port)            3456
    set PARAM(CONSOLE.SlaveTimeOut)     600

#
# DISK:
# 
#   We currently support two disk models
#   * HP - an accurate model of the HP 97560 disk drive
#   * Fixed - all disk accesses incur a fixed latency
#

#
# NOTE:
#
# The following parameters are NOT set here in Tcl, since we need
# to know some system limits (max number of CPUs and max number of
# disk unit registers / node) in order to set them. The parameters
# are given default values in params.c. The following comments are
# included just for documentation purposes.
#
#       set PARAM(DISK.NumControllers.<node>) 1
#	set PARAM(DISK.NumUnitsPerController) 128


if {$SIMOS(ISA)=="ALPHA"} { 
    set PARAM(DISK.Model) Fixed
} else  { 
    set PARAM(DISK.Model) HP
}

  #
  # HP-disk specifics
  #
    # All aspects of the HP disk can be sped up. This value is the
    # percentage of the original model that latencies should measure.
    set PARAM(DISK.HP.Scaling)    100 
   
  # 
  # Fixed-disk specifics 
    # All disk accesses take this many milliseconds
    set PARAM(DISK.Fixed.Latency)    6

# 
# ETHERNET:
# 
#   We only have one model of ethernet right now.
# 
    if {!$SIMOS(RestoringCpt)} {
        # Number of ethernet controllers
        set PARAM(ETHERNET.Count)  1
    }

    set PARAM(ETHERNET.Model)                  EtherSim
 
    # Hardware ethernet address. Be sure to have a different address
    # when two simulations are running. 
    set PARAM(ETHERNET.EtherSim.Address)   8:1:2:3:4:60

    # The machine that is running ethersim
    set PARAM(ETHERNET.EtherSim.Hostname)     localhost 

    # The port to which ethersim will communicate
    set PARAM(ETHERNET.EtherSim.Port)              3232

    # For determinism you will need to make ethernet inactive. A randomly
    # arriving packet can skew the run.
    set PARAM(ETHERNET.EtherSim.Active)              no  
    
#
# MEMORY SYSTEM:
# 
#   Models include:
#   * BusUma     - uniform memory access time with bus contention,
#                  snoopy caches, writeback buffers, and an 
#                  out-of-order split transaction bus.
#   * Numa       - Similar to BusUma, but with latencies dependent on
#                  where memory is found.
#   * Perfect    - Models a zero access time memory system
#   * Flashlite  - Cycle accurate model of the FLASH memory system
#

    if {!$SIMOS(RestoringCpt)} {
        # Memory size in megabytes
        set PARAM(MEMSYS.MemSize)  32
    }

    set PARAM(MEMSYS.Model)              BusUma

 #
 # Perfect paameters
 #

    # The latency (in ns) of a memory request (currently must be zero)
    set PARAM(MEMSYS.Perfect.Latency)         0
 #
 # BusUma parameters
 #

    # The maximum bandwith (in MB/s) that the bus can support
    set PARAM(MEMSYS.BusUma.BusBW)         1200

    # Total time (in ns) to fetch a cache line from memory in an unloaded system
    set PARAM(MEMSYS.BusUma.MemCycleTime)   500

    # The time (in ns) to get data out of another CPU's cache if it is dirty there.
    # Overall time for a dirty miss will be (MemCycleTime + DirtyPenalty) 
    # in an unloaded system.   
    set PARAM(MEMSYS.BusUma.DirtyPenalty)   250

    # Total time (in ns) to issue an upgrade in an unloaded system.
    set PARAM(MEMSYS.BusUma.UpgradeTime)    400

    # The number of memory units (banks).  Different memories can be servicing
    # requests simultaneously if the requested data is in different memory units.
    set PARAM(MEMSYS.BusUma.NumMemories)      1

############
    #
    # Numa parameters
    #

    # The number of memories/directory controllers in the system. The
    # value should lie in the range of 1 to "NUM_CPUS". 1 would be 
    # like a bus-based system. "NUM_CPUS" would be a CPU per
    # controller (e.g. FLASH) and anything in between would have
    # clusters of CPUs per controller (e.g. DASH). 
    set PARAM(MEMSYS.Numa.NumMemories)        1 

    # The latency (in ns) for the bus operation from a processor to
    # its local directory controller.
    set PARAM(MEMSYS.Numa.BusTime)           75

    # The time (in ns) it takes the directory controller to do specific
    # operations.

    # PILocalDCTime = occupancy of dc on local miss
    set PARAM(MEMSYS.Numa.PILocalDCTime)     100

    # PIRemoteDCTime = occupancy of local dc on outgoing remote miss
    set PARAM(MEMSYS.Numa.PIRemoteDCTime)    25

    # NILocalDCTime = occupancy of remote dc on remote miss
    set PARAM(MEMSYS.Numa.NILocalDCTime)     350

    # NIRemoteDCTime = occupancy of local dc on incoming remote miss
    set PARAM(MEMSYS.Numa.NIRemoteDCTime)    25

    # Latency (in ns) for the directory controller to fetch a cache
    # line from local memory.
    set PARAM(MEMSYS.Numa.MemTime)           50

    # Fixed latency (in ns) for going between directory controllers,
    # across the network. 
    set PARAM(MEMSYS.Numa.NetTime)          150

    # Granularity (in pages) of striping physical pages across
    # directory controllers. For example, if this is set to 1, memory
    # pages are distributed roundrobin across the cotrollers. The  
    # default (-1) is stripe size of
    # PARAM(MEMSYS.MemSize)/PARAM(MEMSYS.Numa.NumMemories)/PAGE_SIZE. 
    set PARAM(MEMSYS.Numa.StripeSize)       -1

#
# DEBUG:
#
    set PARAM(DEBUG.Port)              2345
    set PARAM(DEBUG.LoopOnError)       yes
# 
# FILES:
# 
#   Where to find and place simulator related files. You will need
#   plenty of disk space for taking checkpoints. 
#
    # When you take a checkpoint, all of the files will end up here. 
    set PARAM(FILES.CptDir)           .

    # The checkpoint files will be named CPT.xxx.count where this is xxx
    set PARAM(FILES.CptTag)           "NOTAG"

    # Turns compression on for the checkpoint memory file
    set PARAM(FILES.CptCompress)    yes

    # Location from which the 
    set PARAM(FILES.MemFileDir)       .
    
    # SimOS looks here for DISKn when mounting under SimOS
    set PARAM(FILES.DevFileDir)       .
   
    # If this is set, cpu log files will be saved as cpu.log.<number>
    set PARAM(FILES.SaveOldCPULogs) yes

    # 
    set PARAM(FILES.FPROMFile)       ""

#
# VISUAL:
#
    # The port to which the SimOS visual interface should connect
    set PARAM(VISUAL.Port)           1865

    # Period in cycles in which SimOS checks the visual interface
    set PARAM(VISUAL.SamplePeriod)   5000000

#
# CLOCK:
#
if {!$SIMOS(RestoringCpt)} {
    # Number of clocks
    set PARAM(CLOCK.Count)  1
}
if {$SIMOS(ISA) == "ALPHA"} {
    set PARAM(CPU.IntrClockFrequency) 1200
} else {
    ### ignored for now
    set PARAM(CPU.IntrClockFrequency) 100
}

#
# HIVE:
#
    if {!$SIMOS(RestoringCpt)} {
    # This sort of belongs in NVRAM... how many cells to boot hive with
        set PARAM(HIVE.NumCells)            1
    }

#
# FPROM
#
# Firmware PROM and firmware RAM
if {$SIMOS(ISA) == "MIPS" || $SIMOS(ISA)=="MIPS32"} { 

    # The size of FPROM in bytes
    set PARAM(FPROM.PROMSize)          16384

    # The size of FRAM in bytes
    set PARAM(FPROM.RAMSize)           32768

    # Whether to let flashlite handle requests to fprom/fram alias zones
    set PARAM(FPROM.UseFL)             0

#
# MAGIC:
#
#  
    set PARAM(MAGIC.SIPSLatency)      1500
    set PARAM(MAGIC.IPILatency)       1000

    # Initial value of the time of day clock (secs since 00:00:00 UTC, 1/1/70)
    # Zero means retrive value using gettimeofday() system call. 
    set PARAM(MAGIC.InitialTime)      0
}

#
# STATS:
#
    set PARAM(STATS.FalseSharing)       no

#
# CLUSTER:
# 
# These parameters deal with connecting multiple SimOS's together
# for network-based applications. This currently is not supported.
#    set PARAM(CLUSTER.File)             ""
#    set PARAM(CLUSTER.Interval)      40000  
#    set PARAM(CLUSTER.NumSimul)          0
#    set PARAM(CLUSTER.Latency)         100
#    set PARAM(CLUSTER.Barrier)         yes 

#
# These only exist when VCS_FAKE is defined
# 
#   set PARAM(MISC.VCSFake)
#   set PARAM(MISC.VCSFake.FileName)


# migration replication variables

if {$SIMOS(ISA) != "ALPHA" && $SIMOS(ISA)!="X86" } { 
set PARAM(MIGREP.Enable) No
set PARAM(MIGREP.Trigger) 12
set PARAM(MIGREP.Reset) 100
set PARAM(MIGREP.MaxKern) 2400
set PARAM(MIGREP.SampleCount) 10
set PARAM(MIGREP.IntrCount) 2
set PARAM(MIGREP.IntrHot) Yes
set PARAM(MIGREP.ZeroOnWrite) Yes
set PARAM(MIGREP.4BitCounters) No
}

### 
### ALPHA parameters
###

if {$SIMOS(ISA) == "ALPHA"} { 
    set PARAM(ALPHA.BootNT) No
    set PARAM(ALPHA.Files.PALCode)  "./osfpal"
    set PARAM(ALPHA.Files.Console)  "./console"
    set PARAM(ALPHA.Files.Kernel)   "./vmunix"

    set PARAM(ALPHA.Files.NT_Firmware) "./arc_fw.exe"
    set PARAM(ALPHA.Files.NT_OSLoader) "./osloader.exe"
  
    # number of instructions fetched, issued, etc., per cycle
    set PARAM(CPU.Epsilon.Width) 1
    # whether to fetch/issue/retire on successive cycles or all in one cycle
    # If Width > 1, then Pipelined must be 1
    set PARAM(CPU.Epsilon.Pipelined) 0
    # Whether to allow speculation down exception path
    set PARAM(CPU.Epsilon.NewTrapStates) 0
    # this must be 1, or interrupts don't get delivered in Epsilon
    set PARAM(CPU.Epsilon.Trap.TrapNotifyInterrupts) 1
    # 0 => to inject exception PC after most recently fetched instruction
    # 1 => to inject exception PC after most recently committed instruction
    set PARAM(CPU.Epsilon.Interrupt.TrapUncommitted) 1
    # whether to allow interrupt PC to be injected during PRIV_OP_REI or to defer
    set PARAM(CPU.Epsilon.Interrupt.AtRei) 1
    # set to unlikely memory address to reduce debugging messages
    set PARAM(CPU.Alpha.Debug.VATranslation) 0xfffffffffffffff0
}