/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/****************************************************************
 * driver.c

 * This file contains the entry points to mshade.  The init functions
 * in this file are responsible for initializing all of the needed
 * data structures.

 * We also try to concentrate the policy #defines in this file.
 * 
 * Author: $Author: blythe $
 * Date:   $Date: 2002/05/29 01:09:10 $
 *****************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include <strings.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/time.h>
#include <fcntl.h>
#include <setjmp.h>

#include "simmisc.h"
#include "annotations.h"
#include "checkpoint.h"

#include "embra.h"
#include "driver.h"
#include "tc.h"
#include "translator.h"
#include "mem_control.h"
#include "callout.h"
#include "main_run.h"
#include "cp0.h"
#include "clock.h"
#include "qc.h"
#include "cache.h"
#include "stats.h"
#include "embra_interface.h"
#include "directory.h"
#include "decoder.h"
#include "stats.h"
#include "clock.h"
#include "simutil.h"
#include "tcl_init.h"
#include "debug.h"
#include "tc_coherence.h"

CptCallback EmbraExecStateCheckpointCB;



/* Globals */

/* Wouldn't it be nice if we lived in a world where compiliers could
   deal with alignment information?  That way maybe our much abused
   typing system in C could stand a ghost of a chance */
#ifdef COMMENTOUT
unsigned PE_space[ ( SIM_MAXCPUS * sizeof(EmbraState) + DEFAULT_PAGESZ)/
                   sizeof(unsigned)];
#endif

EmbraState* EMP;
/*int curr_cpu; */
EmbraState* curEmp;
EmbraParams embra;


jmp_buf embra_env;
struct timeval run_start;
struct timeval run_end;
/* This is necessary to allow the cp0 module to fool the rest of us */
/* into thinking that ASID 0 never runs */
/* It is set in cp0.c */
int quick_ASID[SIM_MAXCPUS];
#if 0 
int EmUseETLB = 0;
int barrCPUs = 0;
int MPinUP = 0;
int useVQC = 0;
int K0FromDevZero = 0;
int alreadyAlloc = 0;
#endif


int* gBarrier = 0;
int* debugBarrier = 0;
int* checkpointBarrier = 0;
int* tnsLock = 0;
int* exitBarrier = 0;
int deschedNumCPUs = -1;

/* XXX - this is really depended on CPUType */
int log2sizeofcputype = 2;


static void EmbraConfigureTC(void);
static void VerifyOffsets(void);


/* On startup the mmu gets initialized, so we must go through
   and zero out the appropriate pages.  We could just rely
   on the fact that qc_map_page won't map pages with annotations,
   but this will make sure kernel addresses are zerod out.
*/

void
EmbraInstallMemAnnotation(VA vAddr) 
{
   uint page = PAGE_NUMBER(vAddr);

   if (embra.emode == EMBRA_PAGE) {
      if (TOTAL_CPUS==1 || embra.MPinUP) {
         int cpu;
         for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {
#ifdef EMBRA_USE_QC64
            qc64_remove_addr(cpu,vAddr);
#else
            EMP[cpu].mmu[page] = 0;
#endif
         }
      } else {
         CPUWarning("Fix InstallMemAnnotations for MPinMP\n");
      }

   } else {
   }
}

C_LINK int _is_mips2(void);
void Embra_Init(int cpuNum, int swtch)
{
   static int embra_initialized;

   /* Should always be up to date */
/*  curr_cpu = cpuNum; */

   VerifyOffsets();

   curEmp = &EMP[cpuNum];

   if( !embra_initialized ) {
      embra_initialized = 1;
      /* Quick runtime way of deciding if we are on an R4000 */

      if( !_is_mips2()  ) {
         CPUPut("Embra only runs on machines that supports at least the mips2 ISA\n");
         exit( 1 );
      }
      EmbraClockInit();


      if( embra.MPinUP ) {
         int i;
         EmbraState *state = &EMP[TOTAL_CPUS];
         for( i = 0; i <= TOTAL_CPUS; i++ ) {

            EMP[i].myNum = i;
            EMP[i].myBit = (1<<i);
            /* Assume that if any cpu is out of slave loop, then they */
            /* all are */ 
            /*if( EMP[TOTAL_CPUS-1].outOfSlaveLoop ) {*/
            if( deschedNumCPUs >= 0 && EMP[i].outOfSlaveLoop ) { 
               state->next = &EMP[i];
               EMP[i].next = &EMP[TOTAL_CPUS];
               state = state->next;
               deschedNumCPUs++;
            }
            if( deschedNumCPUs < 0  ) { 
               if( 1 ) {
                  EMP[i].next = &EMP[(i+1)%(TOTAL_CPUS+1)];
                  /* Either C handles mod wierd, or I learned them wrong */
                  if( i == 0 )
                     EMP[i].prev = &EMP[TOTAL_CPUS];
                  else
                     EMP[i].prev = &EMP[(i-1)%(TOTAL_CPUS+1)];
               } else { 
                  /* Then we must be booting so only add CPU 0 */
                  EMP[0].next = &EMP[TOTAL_CPUS];
                  EMP[TOTAL_CPUS].next = &EMP[0];
               }
            }
         }
         /*
          * figure out the backpointer in the doubly linked list
          */
         ASSERT( EMP[TOTAL_CPUS].next != &EMP[TOTAL_CPUS]);
         for(state = &EMP[TOTAL_CPUS]; !state->next->prev;state = state->next) {
            state->next->prev = state;
         }

      } else {
         EMP[cpuNum].myNum = cpuNum;
         EMP[cpuNum].myBit = (1<<cpuNum);
      }


      gBarrier          = ZMALLOC(256,"Embra::gBarrier");
      debugBarrier      = ZMALLOC(256,"Embra::debugBarrier");
      checkpointBarrier = ZMALLOC(256,"Embra::checkpointBarrier");
      exitBarrier       = ZMALLOC(256,"Embra::exitBarrier");
      tnsLock           = ZMALLOC(256,"Embra::tnsLock");
   }  
    

   Embra_Clock_Init(cpuNum);

   /* Initialize translation caches & space for dynamic interface code */
   EmbraConfigureTC();

   /* Initialize interface code and register allocation stuff */
   Translator_Init();

   /* Initialize maxInGroup */
   DecoderInit();

   Stat_Init();

   emSMHT = ZMALLOC(TOTAL_CPUS * sizeof(EmSMHT),"Embra:SMHT");
 
   TCcoherence_init(SIM_MEM_ADDR(0));
   Cache_Init(cpuNum);
   Em_Tlb_Init(cpuNum, swtch);

   Directory_Init();
  
   Cache_Init(cpuNum);

   if (cpuNum == 0) {
      if (embra.emode == EMBRA_PAGE) {
         AnnFMInit(DEFAULT_PAGESZ);
      } else {
         /* embra.emode == EMBRA_CACHE */
         AnnFMInit(SCACHE_LINE_SIZE);
      }
      if (!swtch) {
         AnnCommonSetup();
      }
   }
  
   if( embra.MPinUP ) {
      /* XXX - Note the space for the extra processor is not actualy */
      /* mapped shared. It should be allocated elsewhere */
      /* The mythical extra processor just holds the callback address */
      EMP[TOTAL_CPUS].PC = (Reg)EmEventPoll;
      EMP[TOTAL_CPUS].R[31] = (Reg)EmEventPoll;
      /* This needs to be set for the code in main_run which tries to do a */
      /* lookup on the PC, but it is a backdoor, so that look up will */
      /* fail.   May want to check for backdoor directly in that code */
      EMP[TOTAL_CPUS].mmu = EMP[0].mmu;
      /* Have to activate this processor */
      EMP[TOTAL_CPUS].outOfSlaveLoop = 1;
   }
}


void Init_Proc_State(int cpu )
{
   EMP[cpu].Sdhit_count = 0;
   EMP[cpu].Sihit_count = 0;
   EMP[cpu].jumpPC = (uint)continue_run_without_chaining;
   /* Shave 32 bytes off so routines called by continue_run can */
   /* store into it and continue_run itself can store 4 words */

   if((embra.emode == EMBRA_PAGE)||(!embra.useVQC))
      EMP[cpu].Ssreg2 = 0x7fffffff;
}

/* This setjmp allows us to unwind the stack (e.g. after we've flushed
 * the translation cache, taken exceptions, etc.) and return to
 * running in the TC
 */
jmp_buf Embra_Run_Setjmp;

/* We call this routine to unwind the stack and continue running
 * in the TC
 */
void ReenterTC(EmbraState *emp)
{
  curEmp = emp;
  longjmp(Embra_Run_Setjmp, 1);
  /* Not Reached */
  ASSERT(0);
}

/* We call this routine to unwind the stack and continue running
 * in the TC
 */
void ReenterTC_CX(EmbraState *emp)
{
  curEmp = emp;
  longjmp(Embra_Run_Setjmp, 2); /* 2 -> do context switch */
  /* Not Reached */
  ASSERT(0);
}


/* This is the entry point to Embra. Embra_Init should be called */
/* before calling this function */
void Embra_Run( int cpuNum, int clobber_machine_regs )
{
  /* Call the main run routine which does translation on the fly. */
  /* Note that the stack grows down, so we start at the top */
   if( embra.MPinUP ) {
      int cpu;
      for( cpu = 0; cpu <= TOTAL_CPUS; cpu++ ) {
         Init_Proc_State(cpu);
         CPUPrint("%d entering TC at 0x%x\n", cpu, EMP[cpu].PC);
      }
      EMP[TOTAL_CPUS].jumpPC = (Reg)EmEventPoll;
   } else {
      Init_Proc_State(cpuNum);
      CPUPrint("%d entering TC at 0x%x\n", cpuNum, EMP[cpuNum].PC);
   }

   ASSERT(embra.emode == EMBRA_PAGE ||embra.sequential || EMP[cpuNum].outTC );
   ASSERT( (EMP[cpuNum].PC & 0x3) == 0 );
   /* CPUWarning("EMBRA: entering TC \n"); */
   if( clobber_machine_regs ) {
      gettimeofday(&run_start);
      curEmp = &EMP[cpuNum];
      /* Save where we are; we return here on a ReenterTC */
      if (setjmp(Embra_Run_Setjmp) != 2)
	/* Enter TC - never returns*/
	EnterTC(curEmp);
      else
	EnterTC_CX(curEmp); /* Enter TC and switch */
      /* Never reached */
      ASSERT(0);
   }
}

void
ProcRemove( int cpuNum )
{
   ASSERT( embra.MPinUP );
   ASSERT( cpuNum < TOTAL_CPUS );
   ((EmbraState*)EMP[cpuNum].prev)->next = EMP[cpuNum].next;
   ((EmbraState*)EMP[cpuNum].next)->prev = EMP[cpuNum].prev;
   /* Aid Debugging -- dont reset next because I need it to schedule */
   /* the next guy */
   EMP[cpuNum].prev = 0;
}
void
ProcInsertFirst( int cpuNum )
{
   ASSERT( embra.MPinUP );
   ASSERT( cpuNum < TOTAL_CPUS );
   EMP[cpuNum].next = EMP[TOTAL_CPUS].next;
   EMP[cpuNum].prev = &EMP[TOTAL_CPUS];
   ((EmbraState*)EMP[TOTAL_CPUS].next)->prev = &EMP[cpuNum];
   EMP[TOTAL_CPUS].next = &EMP[cpuNum];
}

void 
ProcInsert( int cpuNum )
{
   EmbraState *t = &EMP[TOTAL_CPUS];
   ASSERT( cpuNum < TOTAL_CPUS );
   ASSERT( !EMP[cpuNum].prev );
   while (cpuNum > t->next->myNum ) {
      t = t->next;
   }
   EMP[cpuNum].next = t->next;
   EMP[cpuNum].prev = t;
   t->next->prev = & EMP[cpuNum];
   t->next = & EMP[cpuNum];
}


int
ProcListEmpty(void)
{
   ASSERT( embra.MPinUP );
   return EMP[TOTAL_CPUS].next == &EMP[TOTAL_CPUS];
}

static SimTime stallStart[NUM_MODES][SIM_MAXCPUS];
static CPUMode stallMode[SIM_MAXCPUS]; /* Sanity Check */


/* **********************************************
 * Descheduling to speed up Embra boot
 * **********************************************/


void EmbraPromReleaseInit(void)
{
   deschedNumCPUs = 0;
}

void EmbraPromRelease(void *p1, void *p2)
{
   int i;
   CPUWarning("Releasing CPUs. \n");
   for(i=0;i<TOTAL_CPUS;i++) {
      if( !EMP[i].outOfSlaveLoop && sim_misc.launchAddr[i]) {
         CPUWarning("EmbraPromRelease, launching %i \n",i);
         deschedNumCPUs++;
         ProcInsert(i);
      }
   }
}




/* ******************************************************************
 * EmbraConfigureTC
 * ******************************************************************/

#define LOG_TC_USER_SIZE 22
#define LOG_TC_KERN_SIZE 20
#define LOG_TC_GLUE_SIZE 12

#define TCFLUSH_USER 0x0
#define TCFLUSH_KERN 0x1

#define TC_USER_NUM (1<<LOG_TC_USER_SIZE)
#define TC_KERN_NUM (1<<LOG_TC_KERN_SIZE)
#define TC_GLUE_NUM (1<<LOG_TC_GLUE_SIZE)

#define TC_USER_SIZE (TC_USER_NUM * 4 )
#define TC_KERN_SIZE (TC_KERN_NUM * 4 )
#define TC_GLUE_SIZE (TC_GLUE_NUM * 4 )

#define TC_ANNOTATION_BUFFER (32*1024)

#define MIPS_COMPOSE_I_OP(opCode, rt, rs, immed) ((opCode) << 26 | (rs) << 21 | (rt) << 16 | ((immed) & 0xffff ))
#define TC_BREAKOPCODE  MIPS_COMPOSE_I_OP(cop0_op,0,mfc_op,0);

/* Note we also allocate space for our dynamically
 * generated interface code (see main_run.c) as
 * well as the actual translation caches;
 * we hope that these are within jump range
 */
static void EmbraConfigureTC(void)
{
   int tcSize[3];
   int tcAnnSize[3];
   int pctcSize[3];
   Inst breakOp = TC_BREAKOPCODE;

   /*
    * init TC
    */
   
   tcSize[0] = TC_USER_SIZE;
   tcSize[1] = TC_KERN_SIZE;
   tcSize[2] = TC_GLUE_SIZE;
   tcAnnSize[0] = TC_ANNOTATION_BUFFER;
   tcAnnSize[1] = TC_ANNOTATION_BUFFER;
   tcAnnSize[2] = 2;
   pctcSize[0] = TC_USER_SIZE / (4*8);
   pctcSize[1] = TC_KERN_SIZE / (4*8);
   pctcSize[2] = 2;
   
   TC_init(3,tcSize,pctcSize,tcAnnSize,breakOp);

 }



/* This clears all data structures associated with a translation chache */
void Clear_Translation_State(int cache )
{
   int i;

   /* Need to clear (now stale) return addresses from inside CPU state */
   /* structures */ 
   for( i = 0; i < TOTAL_CPUS; i++ ) {
      if( EMP[i].stalled ) {
         EMP[i].jumpPC = (uint)(void*)continue_run_without_chaining;
         /*EmContinueStall;*/
      } else {
         EMP[i].jumpPC = (uint)continue_run_without_chaining;
      }
   }
   
   if (cache==TCFLUSH_ALL) { 
      /*
       * conflict detected. flush everything.
       * Only at this point can be clear the tccoherence information
       * XXX maybe we should split it by TC cache
       */
      TCcoherence_flush();
      /* Note we don't want to flush our dynamic code!!
       * Only flush User and Kernel TC's
       */
      TC_flush(TCFLUSH_USER);
      TC_flush(TCFLUSH_KERN);
   }
   else {
     TC_flush(cache);
   }
}

/*****************************************************************/

/* Debugging function called from continue_run */
void print_pc( int cpuNum, unsigned pc )
{
   if( EMP[cpuNum].outOfSlaveLoop ) {
      CPUPrint("%d 0x%x\n", EMP[cpuNum].myNum, pc );
      fflush( stdout );
   }
}

void AssertNotStalled(int cpuNum)
{
   VASSERT(!EMP[cpuNum].stalled, ("CpuNum %d\n", cpuNum) );
}

/* This is only used when simulating R3k locking */
/* It doesn't work anymore because of cpuNum */
void TNS( int cpuNum )
{
   int retval;
   volatile int* lock_ptr;
   lock_ptr = (volatile int*)(EMP[cpuNum].R[4]);
   if ( *lock_ptr & 1 ){
      retval = 0;
   } else {
      *lock_ptr = EMP[cpuNum].R[8];
      retval = 1;
   }
   EMP[cpuNum].R[8] = retval;
}

/* Called when a checkpoint is requested.*/
void EmbraCheckpoint(int cpuNum)
{
   int i;
   VA oldPC[SIM_MAXCPUS];
   ASSERT( cpuNum==0);
   for (i=0;i<TOTAL_CPUS;i++) { 
      oldPC[i] = EMP[i].PC;
      if( IS_BACKDOOR(EMP[i].PC) ) {
         /* PC was in the backdoor. In embra, this can only be the
          * case for the processor requesting the checkpoint. 
          * We save the RA rather than the PC
          */
       EMP[i].PC  = EMP[i].R[REG_RA];
      }
      if (IN_BD(EMP[i].PC)) {
         if ( EmbraAnnType() == ANNFM_PC_TYPE) {
            CPUError("CANNOT TAKE CHECKPOINT IN A BRANCH DELAY with a post-pc annotation -- at least not now \n");
         } 
         EMP[i].PC = CLEAR_BD(EMP[i].PC)-INST_SIZE;
      } else { 
         if (i==CPUVec.CurrentCpuNum() &&
             EmbraAnnType()== ANNFM_PC_TYPE ) {
            EMP[i].PC += INST_SIZE;
         }
      }  
   }

   Simcpt_Checkpoint(CPT_SAVE, NULL);
   CPUWarning("\n-> Simcheckpoint: Returning from checkpoint save...\n");
   for (i=0;i<TOTAL_CPUS;i++) {
      EMP[i].PC = oldPC[i];
   }                         
}                     


/* *********************************************************************
 * Embra_DoAnn: (TC callout) 
 * Handles PC annotations
 * *********************************************************************/
void Embra_DoAnn( int cpuNum) 
{
   VA annAddr = CLEAR_BD(EMP[cpuNum].PC);
   AnnPtr aptr;
   ASSERT (curEmp->myNum==cpuNum);
#if defined(SIM_MIPS64)
   if (IS_CKSEG0(annAddr)) {
      annAddr = CKSEG0_TO_XKPHYS(annAddr);
   }
#endif
   aptr = AnnFMLookup(annAddr,ANNFM_PC_TYPE);
   ASSERT(aptr);
   /* 
    * Call EmbraAnnExec to trap the case where
    * the annotation has side-effects
    */
   EmbraAnnExec(cpuNum,aptr,ANNFM_PC_TYPE);
}
void Embra_DoPrePCAnn( int cpuNum) 
{
   VA annAddr = CLEAR_BD(EMP[cpuNum].PC);
   AnnPtr aptr;
   ASSERT (curEmp->myNum==cpuNum);
   aptr = AnnFMLookup(annAddr,ANNFM_PRE_PC_TYPE);
   ASSERT(aptr);
   /* 
    * Call EmbraAnnExec to trap the case where
    * the annotation has side-effects
    */
   EmbraAnnExec(cpuNum,aptr,ANNFM_PRE_PC_TYPE);
}

static void VerifyOffsets(void)
{
   /* checking a couple of the fields of CPUState */

   ASSERT(  GP_OFF == offsetof(CPUState,R));
   ASSERT(  FP_OFF == offsetof(CPUState,FPR));
   ASSERT(  FCR_OFF == offsetof(CPUState,FCR));
   ASSERT(  CP0_OFF == offsetof(CPUState,CP0));
   ASSERT(  PC_OFF == offsetof(CPUState,PC));
   ASSERT(  HI_OFF == offsetof(CPUState,HI));
   ASSERT(  LO_OFF == offsetof(CPUState,LO));
   ASSERT(  CCD_OFF == offsetof(CPUState,cycleCountdown));
   ASSERT(  BCCD_OFF == offsetof(CPUState,blockCycleCountdown));
   ASSERT(  TQ_OFF == offsetof(CPUState,timeQuantum));
   ASSERT(  MMU_OFF == offsetof(CPUState,mmu));
   ASSERT(  CACHE_OFF == offsetof(CPUState,cache_tag));
   ASSERT(  SDHIT_OFF == offsetof(CPUState,Sdhit_count));
   ASSERT(  SIHIT_OFF == offsetof(CPUState,Sihit_count));
   ASSERT(  SSTACK_OFF == offsetof(CPUState,Sstack_base));
   ASSERT(  SSREG2_OFF == offsetof(CPUState,Ssreg2));
   ASSERT(  SORIGSTACK_OFF == offsetof(CPUState,Sorig_stack));
   ASSERT(  MYNUM_OFF == offsetof(CPUState,myNum));
   ASSERT(  NEXT_OFF == offsetof(CPUState,next));
   ASSERT(  OLDPC_OFF == offsetof(CPUState,oldPC));
   ASSERT(  JUMPPC_OFF == offsetof(CPUState,jumpPC));
   ASSERT(  CALL_OFF == offsetof(CPUState,eventQueueTimePtr));
   ASSERT(  HICC_OFF == offsetof(CPUState,cycleCount));
   ASSERT(  LOCC_OFF == offsetof(CPUState,cycleCount)+4);
   ASSERT(  STALLED_OFF == offsetof(CPUState,stalled));
   ASSERT(  CACHE_AX_OFF == offsetof(CPUState,cache_ax));
   ASSERT(  LLCONTENTS_OFF == offsetof(CPUState,LLContents));
   ASSERT(  LLADDR_OFF == offsetof(CPUState,LLAddr));
   ASSERT(  HACKADDR_OFF == offsetof(CPUState,hackedSavedVaddr));
   ASSERT(  LLBIT_OFF == offsetof(CPUState,LLBit));
   ASSERT(  FPLOADED_OFF == offsetof(CPUState,fpLoaded));
   ASSERT(  OUTTC_OFF == offsetof(CPUState,outTC));
   ASSERT(  QCRA_OFF  == offsetof(CPUState,qcra));


}