/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/**************************************************************************
*      File:           main_run.c
*
* This code is called once to generate the main simulator loop and
* assorted other routines. It is a semi-platform-independent rewrite
* of the old MIPS main_run.s. Of course, we could also just make a
* platform-independent MIPS assembler, or write it in some intermediate
* representation.
*
* I have also added in the callout code. It is easier to generate
* everything in one place. Also we avoid name-space pollution with
* the register variables a0, a1, etc..
*
* In this implementation, assembly routines have become C routines which
* generate the desired code at translator init time.
*
*
* To-do: there are a lot of repulsive mips-isms in this code, most
*	 notably that unfortunate t9 convention. These need to be
*	 eliminated and hidden in the vcode interface. Register
*	 allocation needs to be re-thought. RA needs to be re-thought.
*	 much to be done to make this truly portable. However, for now
*	 we at least have a possibility of generating code for other
*	 architectures.
*
* $author$
* $date$
***************************************************************************/


#include "c_port.h"
#include "mips_arch.h"		/* MIPS architecture specification */
#include "embra.h"
#include "callout.h"		/* useful macros for common code sequences */
#include "main_run.h"
#include "mem_control.h"
#include "cp0.h"
#include "debug.h"
#include "tc.h"
#include "translator.h"
#include "driver.h"
#include "qc.h"
#include "vcode.h"		/* vcode types aXSnd macros */

v_code *Main_Run_Buf;		/* Pointer to space for our generated   *
				 * code. Allocated in tc.c		*/
int	Main_Run_Buf_Size;	/* Size of code buffer */


/* Guard against calls to uninitialized functions */
static void bad(void)
{
  CPUError("Embra: Call to uninitialized dynamic routine\n");
  ASSERT(0);
}

vfptr 	EnterTC=(vfptr) bad,		/* Pointers to generated routines */
	EnterTC_CX=(vfptr) bad,
	IncCCasm=(vfptr) bad,
	GeneralEmEventPollasm= (vfptr) bad,
	EmEventPoll=(vfptr)bad,
	UPperiodic_callout=(vfptr)bad,
	Embra_CX=(vfptr)bad,
	Embra_CX_nochain=(vfptr)bad,
	continue_run_without_chaining=(vfptr)bad,
	continue_run=(vfptr)bad,
	SpillFP=(vfptr)bad,
	RestoreFP=(vfptr)bad,
	callout=(vfptr)bad;


/* Memory reference wrappers */
mr_ptr mem_ref_wrapper=(mr_ptr)bad;
mar_ptr	phys_mem_ref_wrapper=(mar_ptr)bad,
	pa_mem_ref_wrapper=(mar_ptr)bad;

mar_ptr QC64HashFunc=(mar_ptr)bad,
    Em_dynPQCdsh=(mar_ptr)bad,
    Em_dynPQCdex=(mar_ptr)bad,
    Em_HackedIPageMMUQC=(mar_ptr)bad;

/* simple static symbol table to preserve my sanity */

typedef struct main_run_sym {
  char *name;
  void *addr;
} main_run_sym;

main_run_sym main_run_syms[] = {
	"Bad", (void *) &bad,
 	"EnterTC", (void *) &EnterTC,
	"EnterTC_CX",(void *) &EnterTC_CX,
	"IncCCasm",(void *) &IncCCasm,
	"GeneralEmEventPollasm",(void *) &GeneralEmEventPollasm,
	"EmEventPoll",(void *) &EmEventPoll,
	"UPperiodic_callout",(void *) &UPperiodic_callout,
	"Embra_CX",(void *) &Embra_CX,
	"Embra_CX_nochain",(void *) &Embra_CX_nochain,
	"continue_run_without_chaining",
	(void *) &continue_run_without_chaining,
	"continue_run",(void *) &continue_run,
	"SpillFP",(void *) &SpillFP,
	"RestoreFP",(void *) &RestoreFP,
	"callout",(void *) &callout,
	"mem_ref_wrapper",(void *) &mem_ref_wrapper,
	"phys_mem_ref_wrapper",(void *) &phys_mem_ref_wrapper,
	"pa_mem_ref_wrapper",(void *) &pa_mem_ref_wrapper,
	"QC64HashFunc",(void *) &QC64HashFunc,
	"Em_dynPQCdsh",(void *) &Em_dynPQCdsh,
	"Em_dynPQCdex",(void *) &Em_dynPQCdex,
	"Em_HackedIPageMMUQC",(void *) &Em_HackedIPageMMUQC
};


extern v_reg_t VREGS[];		/* Allocated registers from translator.c */
extern v_reg_t FVREGS[];

static v_reg_t zero, sp, ra, a0, a1, a2, a3, s2,
					/* registers we use */
  t0, t1, t2, t3, t4, t7, t8, t9,
  v0,v1,
  vss_base,			/* = curEmp = EMP[curcpu] */
  clock_reg,			/* clock */
  dhit_reg,			/* cache registers */
  ihit_reg,
  qc_reg,			/* registers for memory addr quick check */
  mmumask_reg,
  mmu_reg,
  sim_t1, sim_t2, sim_t4,
  branchreg,
  
  pc_reg;			/* simulated PC */

/* Interfaces to several routines we call or call out to
 * This should be cleaned up
 */

extern void VC_Allocate_Regs(void);	/* Allocate registers in VREGS[] */
extern void IncCC(int cpuNum, int inc); /* Increment cycle count...
					 Hmm.... parameters??? */
extern void GeneralEmEventPoll(int cpuNum);
extern void NonReturningProcReturned(void);
extern EmbraState* CEmEventPoll(void);
extern int callout_interval;
extern MA Em_QC64Reload(VA vAddr, int flags );

  
TCA ChainBasicBlock( TCA jump_addr, VA new_pc);

static v_label_t spill_fp_label;	/* labels can't be automatic! ??? ;-( */

/* InterfaceInitRegs(): initialize register variables, which
 * we will use in all of our vcode calls 
 */

/* XXX This register thing needs to be looked at. We need to
 * boil things down to the smallest possible set of registers.
 * Moreover, we need to get rid of MIPS-isms (e.g. t9, calling
 * conventions, etc.) or hide them within the vcode implementation
 * wherever possible.
 */

void InterfaceInitRegs(void)
{
  VC_Allocate_Regs();
  zero		= VREGS[0]; /* bad */
  sp		= VREGS[REG_SP];
  ra		= VREGS[REG_RA];
  a0		= VREGS[REG_A0];
  a1		= VREGS[REG_A1];
  a2		= VREGS[REG_A2];
  a3		= VREGS[REG_A3];
  s2		= VREGS[REG_S2];
  t0		= VREGS[REG_T0];
  t1		= VREGS[REG_T1];
  t2		= VREGS[REG_T2];
  t3		= VREGS[REG_T3];
  /*  t4		= VREGS[REG_T4];  *** not used (yet?) ***/
  /* t7		= VREGS[REG_T7];	*** not used (yet?) ***/
  t8		= VREGS[REG_T8];
  t9		= VREGS[REG_T9];
  v0		= VREGS[REG_V0];
  v1		= VREGS[REG_V1];
  vss_base	= VREGS[VSS_BASE];
  clock_reg	= VREGS[CLOCK_REG];
  dhit_reg	= VREGS[DHIT_REG];
  ihit_reg	= VREGS[IHIT_REG];
  qc_reg	= VREGS[QC_REG];
  mmumask_reg	= VREGS[MMUMASK_REG];
  mmu_reg	= VREGS[MMU_REG];
  sim_t1	= VREGS[SIM_T1];
  sim_t2	= VREGS[SIM_T2];
  sim_t4	= VREGS[SIM_T4];
  branchreg	= VREGS[BRANCHREG];
  pc_reg	= VREGS[PC_REG];

}


/* VLOAD_COMMON_VARS(): load common registers, in this case
 * registers which are used for memory quick check
 */
void VLOAD_COMMON_VARS(void)
{
  v_ldui(qc_reg, vss_base, CACHE_AX_OFF);
  v_ldui(mmumask_reg, vss_base, SSREG2_OFF);
  v_ldui(mmu_reg, vss_base, MMU_OFF);
}


/* EnterTC: we load registers used by Embra, and jump to the
 * main run loop (without chaining, because we are entering from
 * C code rather than translated code)
 */
vfptr GenEnterTC(char *buf, int size, int *used)
{
  v_reg_type arg[1]; /* one argument */

  v_lambda("EnterTC", "%u", arg, V_LEAF, (v_code *) buf, size);

  /* leave some stack space - 256 bytes for now XXX -BL */
  v_addii(sp, sp, -512);
  
  v_movu(vss_base, arg[0]); /* initialize vss_base with curEmp */
  VLOAD_COMMON_VARS();
  v_ldui(clock_reg, vss_base, CCD_OFF);
  v_ldui(dhit_reg, vss_base, SDHIT_OFF);
  v_ldui(ihit_reg, vss_base, SIHIT_OFF);
  REG_LD_OP(pc_reg, vss_base, PC_OFF);
  ASSERT(continue_run_without_chaining != 0);
  v_jpi(continue_run_without_chaining);
  v_nop();
  return v_end(used).v;
}

/* EnterTC_CX: similar to EnterTC, but do a context switch
 * at the end (for MPinUP)
 */
   
vfptr GenEnterTC_CX(char *buf, int size, int *used)
{
  v_reg_type arg[1]; /* one argument */

  v_lambda("EnterTC_CX", "%u", arg, V_LEAF, (v_code *) buf, size);

  /* leave some stack space - 256 bytes for now XXX -BL */
  v_addii(sp, sp, -512);

  /* Original comments follow: */

    /* XXX - This is just here to support the boot */
    /* Now it actually supports the memory system also */
    /* void ReenterTC_CX( EmbraState* ) */
    /* The jumpPC better be a C function or a standard TC entry point. */
	/* For it to be a (more) arbitrary entry point, we need the scheme*/
    /* discussed in phys_mem_ref_wrapper in qc.c */

  /* XXX This thing may have to be changed!! */

  v_movu(	vss_base, arg[0]); /* initialize vss_base with curEmp */

  /* Load current countdown b/c it was adjusted */
  v_ldui(	clock_reg, vss_base, CCD_OFF);
  v_ldui(	s2, vss_base, SSREG2_OFF);
  REG_LD_OP(	pc_reg, vss_base, PC_OFF);
  v_ldui(	dhit_reg, vss_base, SDHIT_OFF);
  v_ldui(	ihit_reg, vss_base, SIHIT_OFF);
  /* This is really only necessary for debugging */
  /* it also probably hoses us somehow!! */
  v_stui(	ra, sp, STOFF_RA);
  /* This gets stored as the jumpPC for this CPU */
  v_ldui(	ra, vss_base, JUMPPC_OFF);
  ASSERT(Embra_CX != 0);
  v_jpi(	Embra_CX);
    
  v_nop();
  return v_end(used).v;
}


vfptr GenIncCCasm(char *buf, int size, int *used)
{
  /* ack! we wanted to save our calling conventions,
   * but I think that might have been hosing us because
   * the original code stores ra in STOFF_RA
   */
  
  v_lambda("GeneralEmEventPollasm", "", NULL, V_LEAF, (v_code *) buf,
	   size);

  v_stui(ra, sp, STOFF_RA);
  /* call C routine to increment (long) cycle count */
  v_ldui(a0, vss_base, MYNUM_OFF);
  v_seti(t9, (unsigned) IncCC);
  v_jalp(ra, t9);
  /* was: v_scallv(IncCC, "%u", a0); */

  /* get low word of cycle count */
  v_ldui(v0, vss_base, LOCC_OFF);
  v_ldui(ra, sp, STOFF_RA);
  
  /* jr ra */
  return v_end(used).v;
}

vfptr GenGeneralEmEventPollasm(char *buf, int size, int *used)
{
  v_lambda("GeneralEmEventPollasm", "", NULL, V_NLEAF, (v_code *) buf, size);
  
  /* This procedure DOES NOT return */
  v_ldui(a0, vss_base, MYNUM_OFF);
  v_scallv(GeneralEmEventPoll, "%u", a0);
  /* This procedure raises an assert of the above procedure returns */
  v_scallv(NonReturningProcReturned, "");

  return v_end(used).v;
}

/* EmEventPoll: Check for pending events and service if necessary.
 */


vfptr GenEmEventPoll(char *buf, int size, int *used)
{

  static v_label_t GeneralEmEventPollasm_label; /* has to be static? */
  static v_label_t restore_proc_label;

  GeneralEmEventPollasm_label = v_genlabel();
  restore_proc_label = v_genlabel();
  
  /* I didn't think up this name */
  
  v_lambda("EmEventPoll", "", NULL, V_LEAF, (v_code *) buf, size);
  
  /* Load callback time ptr */
  v_ldui(t0, vss_base, CALL_OFF);
  /* VSS_BASE = EMP[numCPUs].next -- Don't need old VSS_BASE anymore */
  v_ldui(vss_base, vss_base, NEXT_OFF);
  /* Old 3 instruction sequence to keep track of current cpu...
     la      t1,                   curr_cpu
     lw              t2,           MYNUM_OFF(VSS_BASE)                
     sw      t2,  0(t1)  
        
     */
  /* New 2 insn sequence */
  {
    
  v_seti(t1, ((unsigned)&curEmp) & 0xffff0000); /* XXX this is dumb - fix?? */
  }
  v_orui(t1, t1, ((unsigned)&curEmp) & 0x0000ffff);
  v_stui(vss_base, t1, 0);
  /* Load hi end of callback time */
  v_ldui(t1, t0, 0);
  /* Load hi end of cycle count */
  v_ldui(t2, vss_base, HICC_OFF);
  /* If the most signifigant word of the two do not agree, bail */
  /* GeneralEvEventPollasm does not return */
  v_bnei(t1, t2, GeneralEmEventPollasm_label);
  /* Load lo end of callback time */
  v_ldui(t1, t0, 4);
  /* Load lo end of cycle count */
  v_ldui(t2, vss_base, LOCC_OFF);
  /* t3 = cyclecount - callbacktime */
  v_subu(t3, t2, t1);
  /* Event is probably pending -- service it  */
  /* if (t3 >=0) jp GeneralEventPollasm (does not return) */
  v_bltii(t3, 0, restore_proc_label);
    
  /* GeneralEmEventPollasm_label:    */
  v_label(GeneralEmEventPollasm_label);
  ASSERT(GeneralEmEventPollasm != 0);
  v_jpi(GeneralEmEventPollasm);

  v_label(restore_proc_label);
  /* Load S registers */
  LOAD_COMMON_VARS
  v_ldui(clock_reg, vss_base, CCD_OFF);
  v_ldui(dhit_reg, vss_base, SDHIT_OFF);
  v_ldui(ihit_reg, vss_base, SIHIT_OFF);
  REG_LD_OP(pc_reg, vss_base, PC_OFF);
  v_ldui(t9, vss_base, JUMPPC_OFF);
  ASSERT(Embra_CX_nochain != 0);
  v_jpi(Embra_CX_nochain);
  v_nop();
  return v_end(used).v;
} /* GenEmEventPoll */


    
vfptr GenUPperiodic_callout(char *buf, int size, int *used)
{
  static v_label_t up_event;
  
  v_lambda("UPperiodic)callout", "", NULL, V_LEAF, (v_code *) buf, size);

  up_event = v_genlabel();
  
  /* original comments follow: */
  /* XXX - This is the WRONG solution.  The right way of doing things */
  /* is to figure out why the number of interrupts with and without */
  /* polling is different.  Because we check for interrupts when we */
  /* deliver them and when the SR is changed, we shouldn't need to poll */
  /* Someone needs to route around in clock.c */
  /* This is a fast way of checking to see if any callbacks are pending.*/
  /* The C routine is high on the profile */

  REG_ST_OP(pc_reg, vss_base, PC_OFF);
  v_stui(ra, vss_base, JUMPPC_OFF);
  /* Increment cycle count (int64) */
  v_seti(a0, ((unsigned)&callout_interval)); /* get callout interval */
  v_ldui(a0, a0, 0);
  v_ldui(sim_t1, vss_base, LOCC_OFF);
  v_ldui(sim_t2, vss_base, HICC_OFF);
  v_addu(sim_t4, sim_t1, a0);
  v_ltu(sim_t1, sim_t4, sim_t1);
  v_addu(sim_t2, sim_t2, sim_t1);
  v_stui(sim_t4, vss_base, LOCC_OFF);
  v_stui(sim_t2, vss_base, HICC_OFF);
  /* increment CLOCK register */
  v_addu(clock_reg, clock_reg, a0);
  v_stui(clock_reg, vss_base, CCD_OFF);
  /* load callback time ptr */
  v_ldui(a0, vss_base, CALL_OFF);
  /* compare hi */
  v_ldui(a1, a0, 0);
  v_bneu(a1, sim_t2, up_event);
  v_ldui(a1, a0, 4);
  v_bltu(a1, sim_t4, up_event);
  /* return */
  v_jp(ra);
  v_label(up_event);
  SPILL_FP_IF_ENABLED
  CORRECT_OUTGOING_CC(zero);
  v_setl(t9, ((unsigned) CEmEventPoll));
  v_jalp(ra,t9);
  CORRECT_INCOMING_CC;
  LOAD_COMMON_VARS;
  v_ldui(ra, vss_base, JUMPPC_OFF);

  /* v_jp(ra); */

  return v_end(used).v;
}

/* This is preserved for Historical purposes */

#ifdef EMMETT_TOO_INTENSE
{
    /* We know we are not in a delay slot */
    sw      PC_REG,    PC_OFF(VSS_BASE)
    sw      ra,           JUMPPC_OFF(VSS_BASE)
    lw      a0,           callout_interval
    /* EMP[0].cycleCountdown += callout_interval */
    addu    CLOCK_REG, a0
    /* Load lo end of cycle count */
    lw      t1,           LOCC_OFF(VSS_BASE)
    /* EMP[curr_cpu].cycleCount += timeQuantum */
    /* Actually increase clock by amount used in previous quantum */
    addu    v0,           t1,  a0
    /* If that overflows (changes sign bit which really represents
	both overflow and transition from 31 to 32 bit quantity, but who
	really cares), then do it the long way */
    xor     t1,           v0
    bltzal  t1,           IncCCasm
    /* Both long and short paths store lo part of cycle count back */
    sw      v0,           LOCC_OFF(VSS_BASE)
    /* Load callback time ptr */
    lw      t0,           CALL_OFF(VSS_BASE)
    /* Load hi end of callback time */
    lw      t1,           0(t0)
    /* Load hi end of cycle count */
    lw      t2,           HICC_OFF(VSS_BASE)
    /* If the most signifigant word of the two do not agree, bail */
    bne     t1,           t2, 1f
    
    /* Load lo end of callback time */
    lw      t1,           4(t0)
    /* Load lo end of cycle count */
    lw      t2,           LOCC_OFF(VSS_BASE)
    /* t3 = cyclecount - callbacktime */
    subu    t3,           t2, t1
    /* If the callback time is greater, then likely no callback is pending */
    bltz    t3,           2f
1:
    SPILL_FP_IF_ENABLED
    CORRECT_OUTGOING_CC(zero)
    jal     CEmEventPoll
    /* Certified FP free so return is safe */
    /* Other Sregs the same b/c this is normal call/return */
2:
    CORRECT_INCOMING_CC
    LOAD_COMMON_VARS
    lw      ra,           JUMPPC_OFF(VSS_BASE)
    j       ra
}
#endif
        
vfptr GenEmbra_CX(char *buf, int size, int *used)
{

  static v_label_t IncCC_label;

  v_lambda("Embra_CX", "", NULL, V_LEAF, (v_code *) buf, size);

  IncCC_label = v_genlabel();
  
  /* Context switch for MP_IN_UP */

  /* Ensure that clock and pc are up to date for prev CPU*/
  v_stui(ra, vss_base, JUMPPC_OFF);
  REG_ST_OP(pc_reg, vss_base, PC_OFF);
  /* EMP[curr_cpu].cycleCountdown += timeQuantum */
  v_ldui(t0, vss_base, TQ_OFF);
  v_addu(clock_reg, clock_reg, t0);
  v_stui(clock_reg, vss_base, CCD_OFF);
  v_stui(dhit_reg, vss_base, SDHIT_OFF);
  v_stui(ihit_reg, vss_base, SIHIT_OFF);
  /* Load lo end of cycle count */
  v_ldui(t1, vss_base, LOCC_OFF);
  /* EMP[curr_cpu].cycleCount += timeQuantum */
  /* Actually increase clock by amount used in previous quantum */
  v_addu(v0, t1, t0);
  /* If that overflows (changes sign bit which really represents
     both overflow and transition from 31 to 32 bit quantity, but who
     really cares), then do it the long way */
  v_xoru(t1, t1, v0);
  /* if LT, jump to IncCCasm */
  v_bgeii(t1, 0, IncCC_label);
  ASSERT(IncCCasm != 0);
  v_jalpi(ra, IncCCasm);
  v_label(IncCC_label);
  /* Both long and short paths store lo part of cycle count back */
  v_stui(v0, vss_base, LOCC_OFF);
  SPILL_FP_IF_ENABLED
  /* VSS_BASE = VSS_BASE->next */
  v_ldui(vss_base, vss_base, NEXT_OFF);
  v_setl(t1, ((unsigned) &curEmp));
  v_stui(vss_base, t1, 0);
  /* Load S registers */
  LOAD_COMMON_VARS
  v_ldui(clock_reg, vss_base, CCD_OFF);
  v_ldui(dhit_reg, vss_base, SDHIT_OFF);
  v_ldui(ihit_reg, vss_base, SIHIT_OFF);
  REG_LD_OP(pc_reg, vss_base, PC_OFF);
  v_ldui(t9, vss_base, JUMPPC_OFF);
  ASSERT(Embra_CX_nochain != 0);
  v_jpi(Embra_CX_nochain);

  v_nop();
  return v_end(used).v;
}


vfptr GenEmbra_CX_nochain(char *buf, int size, int *used)
{
  v_lambda("Embra_CX_nochain", "", NULL, V_LEAF, (v_code *) buf, size);

  /* XXX BL: I think this whole scheme is broken now... */
  
  /* XXX - By doing a jal here,  we can catch the case where cpu 0
     calls the CX code, and the jumpPC contained in cpu 1 is to a block
     which was chained speculatively and is actually bogus.  In this
     case, the jal will set the RA to continue_run_without_chaining
     which we will check in Chain_To */

  v_jalp(ra,t9);
  v_nop();
  
  return v_end(used).v;
}



extern void SyncInstr(void);

vfptr Gencontinue_run_without_chaining(char *buf, int size, int *used)
{
  v_lambda("continue_run_without_chaining", "", NULL, V_LEAF, (v_code *) buf, size);

  /* XXX BL: I think this may be broken as well now that we 
   * are using the setjmp/longjmp method of entry, but whatever...
   * it doesn't crash at the moment.
   */
  
  /* Pretend we have a frame, because we leave 32w at top of the */
  /* stack for this purpose */

  v_stui(ra, sp, STOFF_RA);
  OUT_OF_TC

#ifdef PRINT_PC
  /* Something like this may be useful in the future for MP debugging */  
    lw      a0, MYNUM_OFF(VSS_BASE)
	move    a1, PC_REG
	jal     print_pc ;
#endif

    REG_ST_OP(pc_reg, vss_base, PC_OFF);

    CORRECT_OUTGOING_CC(zero);
    SPILL_FP_IF_ENABLED;

    /*
     * No chaining a0==0
     */

    v_setu(a0, 0);

#ifdef SIM_MIPS64    
    v_movl(a1, pc_reg);
#else
    v_movi(a1, pc_reg);
#endif
    
    /* XXX UGH!! t9 convention... what to do??? */
    v_setl(t9, ((unsigned) ChainBasicBlock)); 
    v_jalpi(ra,ChainBasicBlock);

    /* XXX HELP!! How do we do this?? Need new vcode operation... */
    /* sync */

    v_jalpi(ra, SyncInstr);
    
    /* actually only need to restore the common variables,not the volatiles */    
    LOAD_COMMON_VARS
    CORRECT_INCOMING_CC
    ENTERING_TC
    v_jp(v0);

    v_nop();
    
    return v_end(used).v;
}

vfptr Gencontinue_run(char *buf, int size, int *used)
{
  v_lambda("continue_run", "", NULL, V_LEAF, (v_code *) buf, size);

  v_stui(ra, sp, STOFF_RA);
  OUT_OF_TC
  REG_ST_OP(pc_reg, vss_base, PC_OFF);
  CORRECT_OUTGOING_CC(zero);
  SPILL_FP_IF_ENABLED

  v_ldui(a0, sp, STOFF_RA);
  v_addui(a0, a0, -2*INST_SIZE);
#ifdef SIM_MIPS64
  v_movl(a1, pc_reg);
#else
  v_movi(a1, pc_reg);
#endif
  /* xxx ugh - more t9 */
  v_setl(t9, ((unsigned )ChainBasicBlock));
  v_jalp(ra, t9);

  LOAD_COMMON_VARS
  CORRECT_INCOMING_CC
  ENTERING_TC

  v_jp(v0);

  v_nop();
  return v_end(used).v;
}

/* *********************************************************
 * SpillFP and RestoreFP can only be called from assembly
 * as they use VSS_BASE
 * !!! Both functions smash SIM_T4. Beware of that one.
 * *********************************************************/

vfptr GenSpillFP(char *buf, int size, int *used)
{
  int i;
  v_lambda("SpillFP", "", NULL, V_LEAF, (v_code *) buf, size);

  /* Save the FP registers */
  for (i = 0; i <= 31; i++) {
    /* XXX This is truly hosed */
#ifdef SIM_MIPS64
    VC_sdc1_op_(FVREGS[i], vss_base, i*8 + FP_OFF);
#else
    v_stfi(FVREGS[i], vss_base, i*4 + FP_OFF);
#endif
  }

  /* we don't use the real FC registers any more, so
     we don't need to do the following:
     
     cfc1 SIM_T4, $0
     sw   SIM_T4, 0*4+FCR_OFF( FPVSS_BASE )
     cfc1 SIM_T4, $30
     sw   SIM_T4, 30*4+FCR_OFF( FPVSS_BASE )
     cfc1 SIM_T4, $31
     sw   SIM_T4, 31*4+FCR_OFF( FPVSS_BASE )

    */

  /* v_jp(ra); */

  return v_end(used).v;
}


vfptr GenRestoreFP(char *buf, int size, int *used)
{
  int i;
  v_lambda("RestoreFP", "", NULL, V_LEAF, (v_code *) buf, size);

  /* Load the FP registers */
  for (i = 0; i <= 31; i++) {
    /* XXX This is truly hosed */
#ifdef SIM_MIPS64
    VC_ldc1_op_(FVREGS[i], vss_base, i*8 + FP_OFF);
#else
    v_ldfi(FVREGS[i], vss_base, i*4 + FP_OFF);
#endif
    
  }
    /* We don't use the real FCR's, so we don't do this
       any more:

       Load floating point control registers 
       lw   SIM_T4, 0*4+FCR_OFF( FPVSS_BASE )
       ctc1 SIM_T4, $0
       lw   SIM_T4, 30*4+FCR_OFF( FPVSS_BASE )
       ctc1 SIM_T4, $30
       lw   SIM_T4, 31*4+FCR_OFF( FPVSS_BASE )
       ctc1 SIM_T4, $31

    */

  /* v_jp(ra); */

  return v_end(used).v;
}    


/* This is sad; we have no way of doing this as yet...
   LEAF(SyncInstr)
   sync
   j ra
   END(SyncInstr)

*/


/* XXX NOTE:
 *  I am inserting the callout stuff here for now because
 *  it is convenient to have it all in one file....
 *  maybe in the future we can come up with a nice way
 *  of doing this....
 */



/* CALLOUT CONVENTION:
   a0 - contains the cpunumber
   a1 - function specific parameter
   a2 - function specific parameter
   a3 - for loads and stores, number of cycles left in the basic block
   All functions do Em_PE[a0].pc = a1; as one of the first operations
*/

extern void Em_MoveFromC0(int cpuNum, Inst instr); /* r4k_cp0.c */
extern void Em_ExceptionReturn(int cpuNum);
extern void Em_CacheOP(int cpuNum, Inst instr);

/* XXX Should really get the type checking right here... */

vfptr target_table[] = {
    0, /* do_periodic_callout */
    (vfptr) Em_ReadTLBEntry,         /* TLBR */
    (vfptr) Em_WriteTLBEntry,        /* TLBW */
    (vfptr) Em_WriteRandomTLBEntry,  /* TLBWR */
    (vfptr) Em_ProbeTLB,             /* TLBP */
    (vfptr) Em_RestoreFromException, /* RFE */
    (vfptr) Em_ExceptionReturn,      /* ERET */
    (vfptr) Em_RaiseC1Unusable,
    (vfptr) Em_MoveToC0,
    (vfptr) Em_RaiseEXCEPTION,
    (vfptr) TNS,
    (vfptr) Embra_SimosDebugBreak,
    (vfptr) Embra_SimosKernDebugBreak,
    (vfptr) Embra_DoAnn,
    0, /*SimulatorLock*/
    0, /*SimulatorUnlock*/
    (vfptr) CountFP,
    (vfptr) Em_MoveFromC0,	     /* MFC0 */
    (vfptr) Embra_DoPrePCAnn,
    (vfptr) Em_CacheOP
};

/* Gencallout: generate code for callouts from translated code */

vfptr Gencallout(char *buf, int size, int *used)
{
  v_lambda("callout", "", 0, V_LEAF, (v_code *) buf, size);

  /* Notice that we CORRECT_CC this is a small expense, but it
   allows callout routines to return to the translation cache via
   ReenterTC.  This (specifically) allows MoveToC0 to uncover and
   take an interrupt */

  OUT_OF_TC;
  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  CORRECT_OUTGOING_CC(a3);
  SPILL_FP_IF_ENABLED; /* XXX - delete ?? */

  v_ldui(a0, vss_base, MYNUM_OFF);
  
 /* XXX It's that old t9 convention... THIS WILL HAVE TO CHANGE - BL
 * Note also that vcode should have a way to access jump tables of
 * C functions;
 */
  v_setl(t8, ((unsigned) target_table));
  v_addu(t9, t8, sim_t2);
  v_ldui(t9, t9, 0);
  v_jalp(ra, t9);
  
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  ENTERING_TC;
  
  /*  j       ra     */
  return v_end(used).v;
}

/* Genmem_ref_wrapper: generate memory reference wrapper;
 * this is an extremely important function
 */

mr_ptr Genmem_ref_wrapper(char *buf, int size, int *used)
{
  v_lambda("mem_ref_wrapper", "", 0,  V_LEAF, (v_code *) buf, size);


  /* a0 - address of reference (except instr case which is blank)
     a1 - new_state
     a2 -
     a3 - cycle count correction
  */
  /* THESE functions are wrappers around memory accesses */
  /* There are two versions for each function, one that */
  /* uses the physically indexed
     quick check (needed for */
  /* cache mode, and possible performance), and one that doesn't */

  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  CORRECT_OUTGOING_CC(a3);
  SPILL_FP_IF_ENABLED;

  v_ldui(a2, vss_base, MYNUM_OFF);
  v_setl(t9, (unsigned) mem_ref);
  v_jalp(ra, t9);
  v_movu(sim_t1, v0); /* translated address expected in sim_t1 */
  
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  
  /*  j     ra */
  return ((mr_ptr) v_end(used).v);
}


mar_ptr Genphys_mem_ref_wrapper(char *buf, int size, int *used)
{
  static v_label_t pmr_label;
  
  v_lambda("phys_mem_ref_wrapper", "", 0, V_LEAF, (v_code *) buf, size);

  pmr_label = v_genlabel();
  
  /* a0 contains virtual address of reference, a2 contains pc */
  /* SIM_T1 contains the K0 address of reference, if possible */
  /* SIM_T2 contains the rewind amount */

  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  SAVE_QC_REWIND;
  SAVE_JUMPPC;
  OUT_OF_TC;
  CORRECT_OUTGOING_CC(a3);
  SPILL_FP_IF_ENABLED;

  v_movu(a2, sim_t1);
  v_ldui(a3, vss_base, MYNUM_OFF);    /* a3 CC correction already saved */
  v_setl(t9, (unsigned) phys_mem_ref);
  v_jalp(ra, t9);
  v_movu(sim_t1, v0);		      /* we need to restore to v0 */

  CORRECT_INCOMING_CC;
  RESTORE_QC_REWIND;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  ENTERING_TC;
  
  /* If c_mem_ref_wrapper returns non-zero issue that address */
  /* This allows access to backdoor data */
  /* Note that instruction misses always rewind the quickcheck */
  /* because we don't fetch instructions from the backdoor */
  v_bneui(sim_t1, 0, pmr_label);
  v_addu(ra, ra, sim_t2);		/* REWIND QUICK CHECK */
  v_addui(ra, ra, 8);			/* 2 more instructions: jal, delay slot */
  v_label(pmr_label);
  v_jp(ra);				/* we need this for label to work */
  v_nop();
  return ((mar_ptr) v_end(used).v);
}
  

mar_ptr Genpa_mem_ref_wrapper(char *buf, int size, int *used)
{
  static v_label_t pamr_label;
  
  v_lambda("pa_mem_ref_wrapper", "", 0, V_LEAF, (v_code *) buf, size);

  pamr_label = v_genlabel();
  
  /* a0 contains virtual address of reference, a2 contains pc */
  /* SIM_T1 contains the K0 address of reference, if possible */
  /* SIM_T2 contains the rewind amount */

  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  SAVE_QC_REWIND;
  SAVE_JUMPPC;
  OUT_OF_TC;
  CORRECT_OUTGOING_CC(a3);
  SPILL_FP_IF_ENABLED;

  v_movu(a2, sim_t1);
  v_ldui(a3, vss_base, MYNUM_OFF);	/* a3 CC correction already saved */
  v_setl(t9, (unsigned) pa_mem_ref);
  v_jalp(ra, t9);

  v_movu(sim_t1, v0);			/* we need to restore to v0 */

  CORRECT_INCOMING_CC;
  RESTORE_QC_REWIND;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  ENTERING_TC;
  /* If c_mem_ref_wrapper returns non-zero issue that address */
  /* This allows access to backdoor data */
  /* Note that instruction misses always rewind the quickcheck */
  /* because we don't fetch instructions from the backdoor */
  v_bneui(sim_t1, 0, pamr_label);
  v_addu(ra, ra, sim_t2);		/* REWIND QUICK CHECK */
  v_addui(ra, ra, 8);			/* 2 more instructions: jal, delay slot */
  v_label(pamr_label);
  v_jp(ra);				/* we need this for label to work correctly */
  v_nop();
  return ((mar_ptr) v_end(used).v);
}


/* New 64-bit stuff from callout.s */

#ifdef EMBRA_USE_QC64

#define HASH_FUNC(_inreg, _treg1, _treg2) \
      dsrl32(_treg2.reg,_inreg.reg,0); \
      v_rshuli(_treg1,_inreg,12); \
      v_xorul(_treg1,_treg1,_treg2);  \
      v_rshuli(_treg2,_inreg,20);  \
      v_xorul(_treg1,_treg1,_treg2);  \
      dsrl32(_treg2.reg,_inreg.reg,25);  \
      v_xorul(_treg1, _treg1, _treg2);  \
      v_andli(_treg1,_treg1,(QC64_NUM_ENTRIES-1)); 
                
mar_ptr GenQC64HashFunc(char *buf, int size, int *used)
{
  v_lambda("pa_mem_ref_wrapper", "", 0, V_LEAF, (v_code *) buf, size);
  HASH_FUNC(a0,v0,v1)
  /*  j    ra */
  return ((mar_ptr) v_end(used).v);
}


/*
 * Em_dynPQdsh - MMU quick check for data access shared (read).
 *    a0 == vAddr of access
 *    a3 == cycle correction if callout.
 *    returns MA is SIM_T1
 */                       


/*
 * Just a few comments here about what is going on.
 *
 * This is the Page Quick Check. We check to make sure that
 * our PC is on the right page. That is, we do a TLB lookup
 * on the virtual page, and hope we hit.
 *
 * Our TLB is hashed, so we hash the virtual address and use it
 * to look up a TLB entry. We check the TLB entry to make sure that
 * it is the entry for our virtual page.
 *
 * If it is, we get the physical page address, add our offset, and
 * we have the physical address.
 *
 * If it isn't, we call out to read the actual page table.
 *
 * Note that pages can be mapped shared(read), exclusive(write),
 * or instruction (read-only) -> right???
 * We have a different quick check for each kind.
 */

/* typedef struct {
 *  VA      vpn;
 *  MA      ma;
 *  uint    writable;
 * }  QC64HashEntry;
 */


mar_ptr GenEm_dynPQCdsh(char *buf, int size, int *used)
{
  static v_label_t pqc_label1, pqc_label2;

  v_lambda("Em_dynPQCdsh", "", 0, V_LEAF, (v_code *) buf, size);

  pqc_label1 = v_genlabel();
  pqc_label2 = v_genlabel();
  
  HASH_FUNC(a0,a2,sim_t1);		/* a2 = hash(a0) */
  
  v_lshui(a2, a2, 4);			/* x 16 */
  v_addul(sim_t4, mmu_reg, a2);		/* offset into TLB array */
  v_ldli(a1, sim_t4, 0);		/* tlb page virtual address */
  v_rshuli(a2, a0, 12);			/* virtual address */
  v_bnel(a2, a1, pqc_label1);		/* go if no match */

  v_andli(a2, a0, DEFAULT_PAGESZ-1);	/* get page offset */
  v_ldui(sim_t1, sim_t4, 8);		/* page physical base address */
  v_addu(sim_t1, sim_t1, a2);		/* add to offset to get real PA */
  v_jp(ra);				/* return */

  v_label(pqc_label1);

  /* 1:              */
   /* Insert PC into state structure and callout to do lookup */

  v_stli(v0, vss_base, PC_OFF);
  /* shouldn't this be store long??? */
  v_stii(ra, vss_base, QCRA_OFF);
  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  CORRECT_OUTGOING_CC(a3);
  v_stli(a0, vss_base, HACKADDR_OFF);
  v_setl(a1, QC64_READ);
  v_setl(t9, ((unsigned long) Em_QC64Reload));
  /* that annoying t9 convention */
  v_jalpi(ra, ((unsigned long) Em_QC64Reload));
  v_beqli(v0, 0, pqc_label2);
  v_movu(sim_t1, v0); /* delay slot??!!! */

  /* shouldn't this be long also ??? */
  v_ldii(ra, vss_base, QCRA_OFF);
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  v_jp(ra);

  v_label(pqc_label2);
  /* 8:                      */

  v_ldii(ra, vss_base, QCRA_OFF);
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;

  /* Because we are in the same segment as TC, and we are jumping to */
  /* an assembly routine, we can just use the bits directly */
  v_ldli(a0, vss_base, HACKADDR_OFF);
  v_setl(a1, MEM_D_SHARED); 

  ASSERT(mem_ref_wrapper != 0);
  v_jpi(mem_ref_wrapper);

  v_nop();
  
  return ((mar_ptr) v_end(used).v);
}

/* exclusive (write) access */

mar_ptr GenEm_dynPQCdex(char *buf, int size, int *used)
{
  v_label_t pqc_label1, pqc_label2;
  
  v_lambda("Em_dynPQCdex", "", 0, V_LEAF, (v_code *) buf, size);

  pqc_label1 = v_genlabel();
  pqc_label2 = v_genlabel();
  
  HASH_FUNC(a0,a2,sim_t1);		/* a2 = hash(a0) */
  
  v_lshui(a2, a2, 4);			/* x 16 */
  v_addul(sim_t4, mmu_reg, a2);		/* offset into TLB array */
  v_ldli(a1, sim_t4, 0);		/* tlb page virtual address */
  v_rshuli(a2, a0, 12);			/* virtual address */
  v_bnel(a2, a1, pqc_label1);		/* go if no match */

  v_andli(a2, a0, DEFAULT_PAGESZ-1);	/* get page offset */

  v_ldui(a1, sim_t4, 12);		/* get writable */
  v_bequi(a1, 0, pqc_label1);		/* go if zero */
  
  v_ldui(sim_t1, sim_t4, 8);		/* page physical base address */
  v_addu(sim_t1, sim_t1, a2);		/* add to offset to get real PA */
  v_jp(ra);				/* return */

  v_label(pqc_label1);

  /* 1:              */
   /* Insert PC into state structure and callout to do lookup */

  REG_ST_OP(v0, vss_base, PC_OFF);
  /* shouldn't this be store long??? */
  v_stui(ra, vss_base, QCRA_OFF);
  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  CORRECT_OUTGOING_CC(zero);
  v_stli(a0, vss_base, HACKADDR_OFF);
  v_setl(a1, QC64_WRITE);	/* fetch writable */
  v_setl(t9, ((unsigned long) Em_QC64Reload));	/* that annoying t9 convention */
  v_jalpi(ra, ((unsigned long) Em_QC64Reload));

  v_beqli(v0, 0, pqc_label2);
  v_movu(sim_t1, v0);

  /* shouldn't this be long also ??? */
  v_ldui(ra, vss_base, QCRA_OFF);
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  v_jp(ra);

  v_label(pqc_label2);
  /* 8:                      */

  v_ldii(ra, vss_base, QCRA_OFF);
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;

  /* Because we are in the same segment as TC, and we are jumping to */
  /* an assembly routine, we can just use the bits directly */
  v_ldli(a0, vss_base, HACKADDR_OFF);
  v_setl(a1, MEM_D_EXCLUSIVE);

  ASSERT(mem_ref_wrapper != 0);
  v_jpi(mem_ref_wrapper);

  v_nop();
  
  return ((mar_ptr) v_end(used).v);
}
  
/*
 * Em_HackedIPageMMUQC 
 *    a0 == vAddr of access
 *    returns MA is SIM_T2
 */                       


mar_ptr GenEm_HackedIPageMMUQC(char *buf, int size, int *used)
{
  static v_label_t mmuqc64_label;

  v_lambda("EM_HackedIPageMMUQC", "", 0, V_LEAF, (v_code *) buf, size);

  mmuqc64_label = v_genlabel();
  
  HASH_FUNC(a0,a2,sim_t2)
  v_lshui(a2,a2,4);
  v_addul(sim_t4,mmu_reg,a2);
  v_ldli(a1,sim_t4,0);
  v_rshuli(a2,a0,12);
  v_bnei(a2, a1, mmuqc64_label);
  v_ldui(sim_t2,sim_t4,8);        
  v_jp(ra);

  /* 1:                      */
  v_label(mmuqc64_label);

  /* Insert PC into state structure */
  REG_ST_OP(a0, vss_base, PC_OFF);            
  STACK_SAVE_REGS;
  SAVE_SHADOW_REGS;
  CORRECT_OUTGOING_CC(zero);
  v_setl(a1, QC64_READ);	/* read-only fetch*/
  v_setl(t9, ((unsigned long)Em_QC64Reload));/* that annoying t9 convention */
  v_jalpi(ra,Em_QC64Reload);
  v_ldui(ra, vss_base,QCRA_OFF);
  CORRECT_INCOMING_CC;
  STACK_RESTORE_REGS;
  RESTORE_SHADOW_REGS;
  v_rshui(v0, v0,12);
  v_lshui(sim_t2, v0, 12);

  /*  j    ra */
  return ((mar_ptr) v_end(used).v);
    
}
    
#endif /* EMBRA_USE_QC64 */

/* GenInterfaceCode(): generate low-level code for Embra.
 * We call a number of routines, each of which dynamically generates
 * code for a particular routine, and set a pointer to the entry
 * point the new routine.
 *
 * Unfortunately, these must be generated in order. Mutual
 * recursion is not possible at this time, unless both routines
 * are generated at the same time.
 */
void GenInterfaceCode(void)
{
  char *buf = (char *) TC_GetTCPtr(  2 );
  char *start = buf;			/* keep track of start for flush */
  int size = 16384;			/* FIX THIS amount of space left */
  int used;				/* amount used by routine */
  
  InterfaceInitRegs();

  
  /* SpillFP is used by SPILL_FP_IF_ENABLED */
  SpillFP = GenSpillFP(buf, size, &used);
  buf += used; size -= used;

  RestoreFP = GenRestoreFP(buf, size, &used);
  buf += used; size -= used;

  GeneralEmEventPollasm = GenGeneralEmEventPollasm(buf, size, &used);
  buf += used; size -= used;
  
  UPperiodic_callout = GenUPperiodic_callout(buf, size, &used);
  buf += used; size -= used;

  IncCCasm = GenIncCCasm(buf, size, &used);
  buf += used; size -= used;

  /* Used by EmEventPoll, etc. */
  Embra_CX_nochain = GenEmbra_CX_nochain(buf, size, &used);
  buf += used; size -= used;

  /* This routine is used by GenEnterTC */
  continue_run_without_chaining =
    Gencontinue_run_without_chaining(buf, size, &used);
  buf += used; size -= used;

  continue_run = Gencontinue_run(buf, size, &used);
  buf += used; size -= used;

  /* Context switch; used by ReenterTC_CX */
  Embra_CX = GenEmbra_CX(buf, size, &used);
  buf += used; size -= used;

  EnterTC = GenEnterTC(buf, size, &used);
  buf += used; size -= used;

  EnterTC_CX = GenEnterTC_CX(buf, size, &used);
  buf += used; size -= used;

  EmEventPoll = GenEmEventPoll(buf, size, &used);
  buf += used; size -= used;

  callout = Gencallout(buf, size, &used);
  buf += used; size -= used;

  mem_ref_wrapper = Genmem_ref_wrapper(buf, size, &used);
  buf += used; size -= used;
  
  phys_mem_ref_wrapper = Genphys_mem_ref_wrapper(buf, size, &used);
  buf += used; size -= used;
  
  pa_mem_ref_wrapper = Genpa_mem_ref_wrapper(buf, size, &used);
  buf += used; size -= used;

#ifdef EMBRA_USE_QC64
  QC64HashFunc = GenQC64HashFunc(buf, size, &used);
  buf += used; size -= used;

  Em_dynPQCdsh = GenEm_dynPQCdsh(buf, size, &used);
  buf += used; size -= used;

  Em_dynPQCdex = GenEm_dynPQCdex(buf, size, &used);
  buf += used; size -= used;
  
  Em_HackedIPageMMUQC = GenEm_HackedIPageMMUQC(buf, size, &used);
  buf += used; size -= used;
#endif

  /* Flush cache in case vcode didn't */
  TC_SetTCNext(2, (TCA) start, (TCA) buf);
  
}

char *main_run_sym_lookup(void *addr)
{
  int i;
  char *result = "unknown";
  void *last = 0;
  void *cur;

  for (i = 0; i < (sizeof(main_run_syms)/sizeof(main_run_sym)); i++) {
    cur = main_run_syms[i].addr;
    if (cur < addr && cur > last) {
      last = cur;
      result = main_run_syms[i].name;
    }
  }

  return result;
}