/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/****************************************************************
 * cpu.c
 * 
 * Main fetch/decode/execute loop and supporting routines. 
 * 
 * $Author: apatti $
 * $Date: 2003/06/24 17:44:47 $
 *****************************************************************/

#include <stdio.h>
#include <limits.h>
#include <string.h>
#include <sys/types.h>
#include <unistd.h>
#include <setjmp.h>
#include "mipsy_simos.h"
#include "addr_layout.h"
#include "simtypes.h"
#include "cpu.h"
#include "cpu_state.h"
#include "sim_error.h"
#include "cp0.h"
#include "fpu.h"
#include "eventcallback.h"
#include "cpu_stats.h"
#include "cpu_interface.h"
#include "hw_events.h"
#include "tcl_init.h"
#include "params.h"
#include "simutil.h"
#include "registry.h"
#include "print_insts.h"
#include "trace.h"
#include "memref.h"
#include "machine_params.h"
#include "opcodes.h"

#ifdef USE_FLASHLITE
#include "flash_interface.h"
#endif

#ifdef MIPSY_MXS
#  include <errno.h>
#  include <stdlib.h>
#  include "ms.h"
#  define IN_MXS(_P) ((_P)->inMXS)
#else 
#  define IN_MXS(_P) (0)
#endif


#ifdef SOLO
#  include "solo.h"
extern int sys_place_range_StallCPUS;
static int isSolo = 1;
#  ifdef FLASHPOINT
#     include "solo_page.h"
#     define BIG_ENDIAN 1
#     include "machine.h"
#     include "memspy_simulator.h"
#     include "mipsy_interface.h"
#  endif
#else
void SoloTclInit(Tcl_Interp *interp) {}
static int isSolo = 0;
#endif

#ifdef SOLO
#define HOST_DATA_ADDR(vAddr, paddr, cpu) (char *)(vAddr)
#else
#define HOST_DATA_ADDR(vAddr, paddr, cpu) \
  (PHYS_TO_MEMADDR(M_FROM_CPU(cpu),paddr)+(IS_REMAPPED_PADDR(paddr,cpu) ? remapVec->NodeAddr[cpu] : 0))
#endif

/*****************************************************************
 * Global CPU Variables 
 *****************************************************************/
CPUState   *PE;                        /* The big daddy of them all */
CPUState   *pePtr[MIPSY_MAX_CPUS];
jmp_buf     jmpEnv;                    /* Used to exit the main loop */
PA          LLAddrs[MIPSY_MAX_CPUS];   /* LL/SC sans caches */
int         numLLactive = 0;           /* LL/SC sans caches */
bool        mipsySyncWhenDone = FALSE;
bool        mipsySkipCaches   = FALSE;
bool        exitMipsy = FALSE;         /* Set this flag in the debugger to 
                                          leave mipsy */
static CPUState *P;                    /* P is always set to current cpu */

SimTime mipsyCurrentTime = 0;

extern int InterpretVerboseDebug(ClientData clientData, Tcl_Interp *interp,
                                 int argc, char *argv[]);
extern void MipsyInitStats(void);

#ifdef DEBUG_DATA_VERBOSE
unsigned long verboseDebugEnabled = 0;
#endif

/* Local CPU Functions */
static Result ReadInstruction(VA, Inst *);
static Result UncachedWrite(VA, PA, void *, RefSize, bool accelerated);
static Result UncachedRead(VA, PA, void *, RefSize);
static void   CPURun(void *);
static void   DoneRunning(void);

#ifdef USE_FLASHLITE
# ifndef FLASHPOINT
typedef uint64 LL;
# endif
extern LL FlashAdvanceTime(LL newInstTime);
/* Advance flashlite notion of time. */
#endif

#ifdef T5_MODEL
int enableVerilogNode;/* This may allow me to enable the verilog
                         node after mipsy initializes itself */
int T5NodeNum;/* Which node is the T5 acting like? */
#endif

#ifdef MIPSY_MXS
static void SwitchSimulators(int cpuNum,EventCallbackHdr *hdr, void *arg);
static EventCallbackHdr switchSimHdr;
int mxs_annotation = 0;
#endif
static uint mxsRunInterval, mipsyRunInterval;


/*****************************************************************
 * EVENT Support
 *****************************************************************/
#define INSTRUCTION_DONE_EVENT() \
 TraceInstruction(P, instr); \
 PRINT_INSTRUCTION(instr); \
 STATS_INC(cpuNum, numInstructions, 1); \
 if (STATS_VALUE(cpuNum, numInstructions) > STATS_VALUE(cpuNum, nextInstrSample)) { \
    INST_SAMPLE_EVENT(MipsyReadTime(cpuNum), cpuNum, P->PC); \
    STATS_INC(cpuNum, nextInstrSample, MS_SAMPLE_INSTR_INTERVAL); \
 }

/*****************************************************************
 * MEMORY ANNOTATION SUPPORT!
 *****************************************************************/
#define CHECK_LD_ANN(_vAddr, _pAddr) \
{  if (annLoads) {        \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_LD_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
   }                         \
}

#define CHECK_ST_ANN(_vAddr,_pAddr) \
{ if (annStores) {         \
      AnnPtr ptr = AnnFMLookup(_vAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
      ptr = AnnFMLookup(_pAddr, ANNFM_ST_TYPE);\
      if (ptr)         \
         AnnExec(ptr); \
 }                         \
}

/*****************************************************************
 * MipsyInit
 *
 *****************************************************************/
void
MipsyInit(void) 
{
   int i;

   if (!strcmp(CACHE_MODEL, "None")) {
      MipsyTurnOffCaches();
   }

   MipsyInitStats();
   MipsyInitFPU();
   PrintInstsInit();

   for (i = 0; i < TOTAL_CPUS; i++) {
#ifndef SOLO
      EnableInterruptCheck(&PE[i], CHECK_FOR_INTERRUPTS_INTERVAL);
#endif
      LLAddrs[i] = (PA) -1;
      PE[i].timerCycleCount = 0;
      PE[i].inMXS = 0;  
   }

#ifdef MIPSY_MXS
   {
      int i;
      for (i=0; i < TOTAL_CPUS; i++) {
         PE[i].st = (struct s_cpu_state *)
            ZMALLOC(sizeof (struct s_cpu_state),"s_cpu_state");
         if (PE[i].st == NULL) {
            perror ("Mipsy - malloc failed");
            ASSERT (0);
         }
         ms_st_init (PE[i].st);
         PE[i].st->mipsyPtr = (void *) (PE + i);
         PE[i].switchToMXS = PE[i].switchToMIPSY = 0;
      }
   }
#endif
}


/*****************************************************************
 * MipsyCycleCount
 * This is entered into the backdoor vector and is used by memstat 
 * to get the time at each entry into the log.
 *****************************************************************/
SimTime
MipsyCycleCount(int cpuNum) 
{
   return MipsyReadTime(cpuNum);
}

/*****************************************************************
 * MipsyCurrentCpuCycleCount
 *
 * This is entered into the detail vector and is used by the OS
 * as the on-chip cycle counter of the T5 COP0.
 * 
 *****************************************************************/
SimTime
MipsyCurrentCpuCycleCount(void)
{
   return MipsyReadTime(P->myNum);
}

/*****************************************************************
 * MipsyInstructionCount
 * 
 *****************************************************************/
SimTime
MipsyInstructionCount(int cpuNum)
{
   return STATS_VALUE(cpuNum, numInstructions);
}

/*****************************************************************
 * MipsyCurrentCpuNum
 * 
 * Anyone can call this from the cpu vector to determine the current
 * cpu.
 *****************************************************************/
int
MipsyCurrentCpuNum(void)
{
   return P->myNum;
}

/*****************************************************************
 * 
 *****************************************************************/
void
MipsyStall(int cpuNum)
{
  PE[cpuNum].cpuStatus = cpu_stalled;
  STATS_SET(cpuNum, stallStart, MipsyReadTime(cpuNum));
}

/*****************************************************************
 * MipsyUnstall
 *
 * Call this from any memory simulators when a processor is no
 * longer stalled. 
 * The initial if test ensures that the CPU can transition to the halted
 * state at any time without having to ensure that no memory
 * request is outstanding.
 *****************************************************************/
void
MipsyUnstall(int cpuNum)
{
   if (PE[cpuNum].cpuStatus == cpu_halted) {
      return;
   }

   if (PE[cpuNum].cpuStatus == cpu_stalled) {
      PE[cpuNum].cpuStatus = cpu_running;
      STATS_ADD_INTERVAL(cpuNum, stallTime, stallStart);
   } else if (PE[cpuNum].cpuStatus == cpu_libc_blocked) {
      return;
   } else if (PE[cpuNum].cpuStatus == cpu_bdoor_stalled) {
      return;
   } else {
      /* Was probably stalled on an uncached_op */
      PE[cpuNum].cpuStatus = cpu_running;
   }
}

/* *****************************************************************
 * Mipsy LL/SC support routines
 * *****************************************************************/

void MipsyClearLockFlag(int cpuNum)
{
   PE[cpuNum].LLbit  = 0;
}

bool MipsyGetLockFlag(int cpuNum)
{
   return PE[cpuNum].LLbit;
}

PA MipsyGetLockAddr(int cpuNum)
{
   return PE[cpuNum].LLAddr;
}

CPUStatus MipsyCPUStatus(int cpuNum)
{
   return PE[cpuNum].cpuStatus;   
}

/*****************************************************************
 * MipsyFinishMemRequests
 *
 * Spin advancing time until all cpus are unstalled.
 *****************************************************************/
void 
MipsyFinishMemRequests(void) 
{
   CPUState *lastP; 
   CPUState *firstP;
   bool somebodyStalled = FALSE;
   int i;

   for (i = 0; i < TOTAL_CPUS; i++) {
      if (PE[i].cpuStatus != cpu_running) {
         somebodyStalled = TRUE;
      }
   }

   firstP = &PE[0];
   lastP  = &PE[TOTAL_CPUS-1];
   P      = lastP;

   while (somebodyStalled) {
      P++;
      if (P > lastP) {
         P = firstP;
         mipsyCurrentTime++;
         EventPollSingleQueue(MipsyReadTime(0));
      } /* Things to do each wrap-around */
      somebodyStalled = FALSE;
      for (i = 0; i < TOTAL_CPUS; i++) {
         if (PE[i].cpuStatus != cpu_running &&
             PE[i].cpuStatus != cpu_idle    && /* idle if it was taken out */
             PE[i].cpuStatus != cpu_halted) {  /* was halted after fault injection */
            somebodyStalled = TRUE;
         }
      }
   }
}

/*****************************************************************
 * PrepareToSwitch
 *
 * This just checks if the current PC value has an annotation. 
 * This is needed in the cpu switching code so that we get a chance 
 * to advance the PC before moving to the next simulator.
 *****************************************************************/
static void
PrepareToSwitch(void)
{
   int cpu;
   
   for (cpu=0; cpu < TOTAL_CPUS; cpu++) {
      CPUState *P = &PE[cpu];
      if (AnnFMLookup(P->PC, ANNFM_PC_TYPE)) {
         CPUWarning("MIPSY: Switching on PC annotation -> advancing PC\n");
         /* advance PC only if current instruction is not a branch thats
            going to be taken */
         if (P->branchStatus == BranchStatus_taken) {
            CPUWarning("CPU %d on branch 0x%x (postPC), keeping it there\n",
                       cpu, P->PC);
         } else {
            P->PC = P->nPC;
            P->nPC += INST_SIZE;
         }
      } else if (AnnFMLookup(P->PC, ANNFM_PRE_PC_TYPE)) {
         if (P->nPC != (PE->PC + INST_SIZE)) {
            CPUWarning("CPU %d on delay slot 0x%x (prePC), backing up to 0x%x\n",
                       cpu, P->PC, P->PC - INST_SIZE);
            P->PC -= INST_SIZE;
         }
      }
   }
}

/*****************************************************************
 * MipsyExit
 * 
 *****************************************************************/
void 
MipsyExit(CPUType exitTo)
{
   PrepareToSwitch();
#ifndef SOLO
   /* Before we exit mipsy, we need to make sure that all outstanding
      memory references have completed. This just advances time until
      all outstanding memory references are complete. This is
      determined to be done when all processors have moved 
    */ 
   MipsySetExitSimulator(exitTo);
   MipsyFinishMemRequests();
#endif
   PrintRealTime("Simulation End");
   /* This kicks us out of the main loop */
   longjmp(jmpEnv, 1);
}

/*****************************************************************
 * ReadInstruction()
 * 
 * Called from the main execution loop each time an instruction 
 * is needed. The first argument is the PC value to read from. 
 * "backdoor" is a way of avoiding going through the cache
 * and memory system to directly access something in our real-life
 * address space (mipsy or simos). This procedure better be as fast as
 * possible!!! The Result returned is just a way of telling the
 * processor whether it has to stall or not (i.e. if there was an icache
 * miss. 
 *****************************************************************/
static Result
ReadInstruction(VA vAddr, Inst *inst)        
{
   Result ret;
   PA pAddr;
   int64 bdoorRetval = 0; 
   uint tlbFlavor = TLB_IFETCH|TLB_READING;
   void *bdoorAddr = 0;

   if (TranslateVirtual(P, vAddr, &pAddr, &tlbFlavor, &bdoorAddr) != SUCCESS)
      return FAILURE;

   if (!tlbFlavor) {
      P->pcVPNcache = PAGE_NUMBER(vAddr);
      P->pcPaddrcache = FORM_ADDR(PAGE_NUMBER(pAddr), 0);

      if (SKIP_CACHES(P)) {
         *inst =*(Inst *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum);
         return SUCCESS;
      }

      ret =  MemRefReadInst(P->myNum, vAddr, pAddr, inst);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "fetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(*inst));

      if (ret != SUCCESS) {
         if ((ret == STALL) || (ret == FAILURE)) {
            P->stalledInst = 0;
            P->cpuStatus = cpu_stalled;
         } else if (ret == BUSERROR) {
            RECORD_EXCEPTION(P, EXC_IBE, E_VEC, vAddr, 
                             P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
         } else {
            CPUWarning("Unknown return value (%d) from ReadICache\n", ret);
         }
      }

      /*
       * The processor can have been idled as a consequence of an annotations
       * For now, we can implement this by checking for the cpuStatus
       */
      if (P->cpuStatus == cpu_idle) {
         P->stalledInst = 0;
         ret = FAILURE;
      } 
      return ret;
   } else {
#ifndef SOLO
      /* this might be one of three things:
       *    the boot prom (provided by flashlite)
       *    the prom slave loop (SimOS magic)
       *    a backdoor call
       */
      if (tlbFlavor & TLB_UNCACHED) {
         /* executing instructions from the prom provided by flashlite
          * or simmagic
          */
         ret =  UncachedRead(vAddr, pAddr, inst, WORD_SZ);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "ufetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(*inst));
	return ret;
      } 

      /* A backdoor  call. Execute it on the real CPU. This */
      /* assumes that all backdoor calls take less than 4 */
      /* arguments. */

      ret = MemRefSync(P->myNum);
      if (ret != SUCCESS) {
         /* Make sure all cached and uncached writes are flushed
          * out of buffers before doing a backdoor call. This 
          * is needed for calls that start I/O.
          */
         return FAILURE;
      }

      SIM_DEBUG(('b', "MIPSY:CPU %d: Backdoor call at PC %#x PA %#x RA %#x\n", 
                 P->myNum, P->PC, pAddr, P->R[31]));

      if (tlbFlavor == TLB_BDOOR_DATA) {
         *inst = *(Inst *)bdoorAddr;
      } else if (tlbFlavor == TLB_BDOOR_FUNC) {
         Result returnFlag;
         
         returnFlag = ((Result (*)(int, uint, uint, unsigned char *))bdoorAddr)
            (P->myNum, vAddr, BDOOR_LOAD_WORD, (unsigned char *)inst);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "bfetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(*inst));

         if (returnFlag == SUCCESS) {
            return SUCCESS;
         } else if (returnFlag == BUSERROR) {
            RECORD_EXCEPTION(P, EXC_IBE, E_VEC, vAddr, 
                             P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
            return BUSERROR;
         } else {
            CPUError("Unknown result type: 0x%x\n", returnFlag);
         }
      } else {
         ASSERT(tlbFlavor == TLB_BDOOR_FUNC_COMPAT);
         bdoorRetval = ((int64 (*)(int,int,int,int))
                        (bdoorAddr))(P->R[4],P->R[5],P->R[6],P->R[7]);
         P->R[2] = bdoorRetval >> 32;
         P->R[3] = bdoorRetval & 0xffffffff;
         *inst = 0; /* NOP */
         P->nPC = P->R[31];
      }
      return SUCCESS;
#endif
#ifdef SOLO
      /* Solo Mipsy has back door calls that need to be handled */
      /* We may need to know our cpu number at this time */
      soloCPUNum = P->myNum;
      bdoorRetval = ((int64 (*)(int,int,int,int))P->PC)
         (P->R[4],P->R[5],P->R[6],P->R[7]);
      P->R[2] = bdoorRetval >> 32;
      P->R[3] = bdoorRetval & 0xffffffff;

      P->nPC = P->R[31];
      *inst = 0; /* NOP */
      STATS_INC(P->myNum, numBdoorInsts, 1);
      return SUCCESS;
#endif
   }
}

/****************************************************************
 * MipsyReadMem
 * 
 * Common routine used by the CPU to read memory.
 *****************************************************************/
Result
MipsyReadMem(VA vAddr, void *data, RefSize size, RefFlavor flavor)
{
   Result ret;
   PA pAddr;
   uint tlbFlavor = TLB_READING;
   void *bdoorAddr = 0;
   
   ret = TranslateVirtual(P, vAddr, &pAddr, &tlbFlavor, &bdoorAddr);
   
   if (ret == SUCCESS) { 
      if (!tlbFlavor) {

         if (flavor & LL_FLAVOR) { 
            P->LLAddr =  pAddr & ~(SCACHE_LINE_SIZE-1);
            if (UNCACHED_LL_SC) {
               LLAddrs[P->myNum] = pAddr & ~(SCACHE_LINE_SIZE-1);
            }
         }
 
         if (SKIP_CACHES(P)) {
            switch (size) {
            case BYTE_SZ:
               *(byte *)data = *(byte *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum);
               break;
            case HALF_SZ:
               *(short *)data = BE2HO_2(*(short *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum));
               break;
            case WORD_SZ:
               *(uint *)data = BE2HO_4(*(uint *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum));
               break;
            case DOUBLE_SZ:
               *(int64 *)data =BE2HO_8(*(int64 *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum));
               break;
            default:
               CPUError("Bad size in MipsyReadMem\n");
               ASSERT(0);
            }
            return SUCCESS;
         }
         
         /* Go through the cache interface */
         switch (size) {
         case BYTE_SZ:
            ret = MemRefReadData(P->myNum, vAddr, pAddr, data, BYTE_SZ, NO_FLAVOR);
            break;
         case HALF_SZ:
            ret = MemRefReadData(P->myNum, vAddr, pAddr, data, HALF_SZ, NO_FLAVOR);
            *(short *)data = BE2HO_2(*(short *)data);
            break;
         case WORD_SZ:
            ret = MemRefReadData(P->myNum, vAddr, pAddr, data, WORD_SZ, flavor);
            *(uint *)data = BE2HO_4(*(uint *)data);
            break;
         case DOUBLE_SZ:
            ret = MemRefReadData(P->myNum, vAddr, pAddr, data, DOUBLE_SZ, flavor);
            *(int64 *)data = BE2HO_8(*(int64 *)data);
            break;
         default:
            CPUError("Bad size in MipsyReadMem\n");
            ASSERT(0);
         }

         if (ret != SUCCESS) { 
oops:
            if ((ret == STALL) || (ret == FAILURE)) {
               P->cpuStatus = cpu_stalled;
            } else if (ret == BUSERROR) {
               RECORD_EXCEPTION(P,EXC_DBE, E_VEC, vAddr, 
                                P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
               return ret;
            } else {
               CPUWarning("Bad return value (%d) from MemRefReadData\n", ret);
            }
         } else {
            /* We hit in the DCACHE */
            CHECK_LD_ANN(vAddr, pAddr);
            STATS_INC(P->myNum, dReads, 1);
         }
      } else {
         if (tlbFlavor & TLB_UNCACHED) {
            ret = UncachedRead(vAddr, pAddr, data, size);
	    if (ret != SUCCESS) {
		P->cpuStatus = cpu_running;
		goto oops;
	    }
            switch (size) {
            case BYTE_SZ:
               *(byte *)data = *(byte *)data;
               break;
            case HALF_SZ:
               *(short *)data = BE2HO_2(*(short *)data);
               break;

            case WORD_SZ:
               *(uint *)data = BE2HO_4(*(uint *)data);
               break;
            case DOUBLE_SZ:
               *(uint64 *)data = BE2HO_8(*(uint64 *)data);
               break;
            default:
               CPUError("Bad size in MipsyReadMem\n");
               ASSERT(0);
            }
#ifdef HWBCOPY
            if ((size == DOUBLE_SZ) && (tlbFlavor == TLB_MSG_SPACE)) ret = SUCCESS;
#endif
         } else if (tlbFlavor == TLB_BDOOR_DATA) {

            STATS_INC(P->myNum, numBdoorInsts, 1);

            switch (size) {
            case BYTE_SZ:
               *(byte *)data = *(byte *)bdoorAddr;
               break;
            case HALF_SZ:
               *(short *)data = *(short *)bdoorAddr;
               break;

            case WORD_SZ:
               *(uint *)data = *(uint *)pAddr;
               break;
            case DOUBLE_SZ:
               *(uint64 *)data = *(uint64 *)bdoorAddr;
               break;
            default:
               CPUError("Bad size in MipsyReadMem\n");
               ASSERT(0);
            }
            return SUCCESS;

         } else {
            Result returnFlag;
            
            ASSERT(tlbFlavor == TLB_BDOOR_FUNC);

            switch (size) {
            case BYTE_SZ:
               returnFlag = ((Result (*)(int, uint, uint, unsigned char *))bdoorAddr)
                  (P->myNum, vAddr, BDOOR_LOAD_BYTE, data);
               break;
            case HALF_SZ:
               returnFlag = ((Result (*)(int, uint, uint, short *))bdoorAddr)
                  (P->myNum, vAddr, BDOOR_LOAD_HALF, data);
               break;
            case WORD_SZ:
               returnFlag = ((Result (*)(int, uint, uint, int*))bdoorAddr)
                  (P->myNum, vAddr, BDOOR_LOAD_WORD, data);
               break;
            case DOUBLE_SZ:
               returnFlag = ((Result (*)(int, uint, uint, uint64 *))bdoorAddr)
                  (P->myNum, vAddr, BDOOR_LOAD_DOUBLE, data);
               break;
            default:
               CPUError("Bad size in MipsyReadMem\n");
               ASSERT(0);
            }
            
            if (returnFlag == SUCCESS) {
               return SUCCESS;
            } else if (returnFlag == BUSERROR) {
               RECORD_EXCEPTION(P, EXC_DBE, E_VEC, vAddr, 
                                P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
               return BUSERROR;
            } else {
               CPUError("Unknown result type: 0x%x\n", returnFlag);
            }
         }
      }
   }
   return ret;
}

/* Used by solo */
Result
SoloReadByte(int cpuNum, VA vAddr, char *data)
{
   return MipsyReadMem(vAddr, (void *)data, BYTE_SZ, NO_FLAVOR);
}


/****************************************************************
 * MipsyWriteMem
 * 
 * Common routine used by the CPU to write memory.
 *****************************************************************/
Result
MipsyWriteMem(VA vAddr, void *data, RefSize size, RefFlavor flavor)
{
   Result ret;
   PA pAddr;
   uint tlbFlavor = TLB_WRITING;
   void *bdoorAddr = 0;

   if (TranslateVirtual(P, vAddr, &pAddr, &tlbFlavor, &bdoorAddr) != SUCCESS) {
      return FAILURE;
   }

   if (flavor == SC_FLAVOR) {
      if (!P->LLbit)
         return SCFAILURE;
   }

   if (!tlbFlavor) {
      /* Special code to handle LL/SC when caches are inactive */
      if (UNCACHED_LL_SC) {
         if (numLLactive) {
            int cpu;
            PA matchAddr = pAddr & ~(SCACHE_LINE_SIZE-1);
            if (P->LLbit) {
               P->LLbit = 0;
               LLAddrs[P->myNum] = (PA) -1;
               numLLactive--;
            }
            for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {
               if (LLAddrs[cpu] == matchAddr) {
                  PE[cpu].LLbit = 0;
                  LLAddrs[cpu] = (PA) -1;
                  numLLactive--;
               }
            }
         }
      }

      if (SKIP_CACHES(P)) {
         switch (size) {
         case BYTE_SZ:
            *(byte *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum)   = *(byte *)data;
            break;
         case HALF_SZ:
            *(short *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum)  = HO2BE_2(*(short *)data);
            break;
         case WORD_SZ:
            *(uint *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum)   = HO2BE_4(*(uint *)data);
            break;
         case DOUBLE_SZ:
            *(uint64 *)HOST_DATA_ADDR(vAddr, pAddr, P->myNum) = HO2BE_8(*(uint64 *)data);
            break;
         default:
            ASSERT(0);
         }
         return SUCCESS;
      }
      
      /* Normal path through the cache interface. */
      switch (size) {
      case BYTE_SZ:
         ret = MemRefWriteData(P->myNum, vAddr, pAddr, 
                               *(byte *)data, BYTE_SZ, NO_FLAVOR);
         break;
      case HALF_SZ:
         ret =  MemRefWriteData(P->myNum, vAddr, pAddr,
                                HO2BE_2(*(short *)data), HALF_SZ, NO_FLAVOR);
         break;
      case WORD_SZ:
         ret = MemRefWriteData(P->myNum, vAddr, pAddr, 
                               HO2BE_4(*(uint *)data), WORD_SZ, flavor); 
         break;
      case DOUBLE_SZ:
         ret =  MemRefWriteData(P->myNum, vAddr, pAddr, 
                                HO2BE_8(*(uint64 *)data), DOUBLE_SZ, flavor);
         break;
      default:
         ASSERT(0);
      }

      if (ret != SUCCESS) { 
         if ((ret == STALL) || (ret == FAILURE)) {
            P->cpuStatus = cpu_stalled;
         } else if (ret == BUSERROR) {
            RECORD_EXCEPTION(P, EXC_DBE, E_VEC, vAddr, 
                             P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]) ;
            return ret;
         } else if (ret == SCFAILURE) {
            /* This is OK, isn't it? */
         } else { 
            CPUWarning("Bad return value (%d) from MemRefWriteData\n", ret);
         }
      } else {
         CHECK_ST_ANN(vAddr, pAddr);
         STATS_INC(P->myNum, dWrites, 1);
      }
      return ret;
   }

   if (tlbFlavor & TLB_UNCACHED) {

      switch (size) {
      case BYTE_SZ:
	 return UncachedWrite(vAddr, pAddr, data, size, (bool)tlbFlavor & TLB_ACCELERATED);
      case HALF_SZ: {
	 short tmp = HO2BE_2(*(short*)data);
	 return UncachedWrite(vAddr, pAddr, &tmp, size, (bool)tlbFlavor & TLB_ACCELERATED);
	 }
      case WORD_SZ: {
	 uint tmp = HO2BE_4(*(uint*)data);
	 return UncachedWrite(vAddr, pAddr, &tmp, size, (bool)tlbFlavor & TLB_ACCELERATED);
	 }
      case DOUBLE_SZ: {
	 uint64 tmp = HO2BE_8(*(uint64*)data);
	 return UncachedWrite(vAddr, pAddr, &tmp, size, (bool)tlbFlavor & TLB_ACCELERATED);
	 }
      default:
         ASSERT(0);
      }
#ifdef HWBCOPY
   } else if (tlbFlavor & TLB_MSG_SPACE) {
      return SUCCESS;
#endif
   } else if (tlbFlavor == TLB_BDOOR_DATA) { 
#ifndef SOLO
      ASSERT(0);
#endif
         switch (size) {
         case BYTE_SZ:
            *(byte *)bdoorAddr = *(byte *)data;
            break;
         case HALF_SZ:
            *(short *)bdoorAddr = *(short *)data;
            break;
         case WORD_SZ:
            *(uint *)pAddr = *(uint *)data;
            break;
         case DOUBLE_SZ:
#ifdef SOLO
            *(uint64 *)pAddr = *(uint64 *)data;
#else
            *(uint64 *)bdoorAddr = *(uint64 *)data;
#endif
            break;
         default:
            ASSERT(0);
         }
      return SUCCESS;
   } else {
      Result returnFlag;
      
      ASSERT(tlbFlavor == TLB_BDOOR_FUNC);

      switch (size) {
      case BYTE_SZ:
         returnFlag = ((Result (*)(int, uint, uint, unsigned char*))bdoorAddr)
            (P->myNum, vAddr, BDOOR_STORE_BYTE, (byte *)data);
         break;
      case HALF_SZ:
         returnFlag = ((Result (*)(int, uint, uint, short*))bdoorAddr)
            (P->myNum, vAddr, BDOOR_STORE_HALF, (short *)data);
         break;
      case WORD_SZ:
         returnFlag = ((Result (*)(int, uint, uint, uint*))bdoorAddr)
            (P->myNum, vAddr, BDOOR_STORE_WORD, (uint *)data);
         break;
      case DOUBLE_SZ:
         returnFlag = ((Result (*)(int, uint, uint, uint64*))bdoorAddr)
            (P->myNum, vAddr, BDOOR_STORE_DOUBLE, (uint64 *)data);
         break;
      default:
         ASSERT(0);
      }

      if (returnFlag == SUCCESS) {
         return SUCCESS;
      } else if (returnFlag == BUSERROR) {
         ASSERT(0);
         RECORD_EXCEPTION(P, EXC_DBE, E_VEC, vAddr, 
                          P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
         return BUSERROR;
      } else {
         CPUError("Unknown result type: 0x%x\n", returnFlag);
      }
   }
   return SUCCESS;
}

Result
SoloWriteByte(int cpuNum, VA vAddr, char data)
{
   return MipsyWriteMem(vAddr, &data, BYTE_SZ, NO_FLAVOR);
}

/*****************************************************************
 * UncachedWrite. 
 *****************************************************************/
static Result
UncachedWrite(VA vAddr, PA pAddr, void *data, RefSize size, bool accelerated)
{
   Result ret;
#ifdef FLASHPOINT
   uint flavor;
   FLASHAddress addr;
   LL storeData;

#endif

   ASSERT ((size == BYTE_SZ) || (size == HALF_SZ) 
           || (size == WORD_SZ) || (size == DOUBLE_SZ));

   /* need to temporarily set cpu_stalled_uncached before MemRefWrite
      because it might block */
   P->cpuStatus = cpu_stalled_uncached;
   ret = MemRefWriteUncached(P->myNum, vAddr, pAddr, data, size, accelerated);

   if (ret != SUCCESS) {
      P->cpuStatus = cpu_stalled_uncached;
   } else {
      P->cpuStatus = cpu_running;

#ifdef FLASHPOINT
      flavor = TLB_UNCACHED;
      addr.ll = SoloV_to_P(P->myNum, vAddr, P->myNum, 0, &flavor); 
      storeData = *((LL *) data);
      
      CPUPrint("Mipsy: cpu %d, Uncached store to 0x%llx, data is %lld\n", 
               P->myNum, addr.ll, storeData);
      
      if(addr.fa.space == PERF) {
         CPUPrint("Mipsy: Perf store!\n");
         if((addr.fa.offset & PERF_FP_MASK) == PERF_FP_ENTER_PROC) {
            Memspy_ProcedureNum newProcedure =
               Memspy_Sim_GetProcedureNum(GetSimulatorMemspyGlobals(),
                                          P->myNum);
            newProcedure += storeData;
            CPUPrint("Mispy: Enter proc, delta = %lld\n", storeData);
            Memspy_Sim_SetProcedureNum(GetSimulatorMemspyGlobals(),
                                       P->myNum, 
                                       newProcedure);

            FP_BinStatsProcedureDelta(P->myNum, storeData);
         }
         if((addr.fa.offset & PERF_FP_MASK) == PERF_FP_NEW_BIN) {
            Memspy_VA app_addr = (Memspy_VA) 
               SoloGetMemoryAddr(storeData & 0xffffffffffLL);
            unsigned length = (unsigned) (storeData >> 52);

            Memspy_Sim_MapPage(GetSimulatorMemspyGlobals(),
                               app_addr, length);
            CPUPrint("Mipsy: Perf Mapping page containing vaddr %lx, paddr %llx to bin %lld, length %u\n", app_addr,
                     storeData & 0xffffffffffLL,
                     (storeData>>40)&0xfff, length);

         }
      }
      
#endif
   }

   CHECK_ST_ANN(vAddr,pAddr);
   STATS_INC(P->myNum, dWrites, 1);

   TraceUncachedDataRef(P, vAddr, pAddr);

   return ret;
}

/****************************************************************
 * UncachedRead
 *****************************************************************/
static Result
UncachedRead(VA vAddr, PA pAddr, void *data, RefSize size)
{
   Result ret;

   ASSERT ((size == BYTE_SZ) || (size == HALF_SZ) 
           || (size == WORD_SZ) || (size == DOUBLE_SZ));

   /* need to temporarily set cpu_stalled_uncached before MemRefRead
      because it might block */
   P->cpuStatus = cpu_stalled_uncached;
   ret = MemRefReadUncached(P->myNum, vAddr, pAddr, data, size);

   if (ret != SUCCESS) {
      P->cpuStatus = cpu_stalled_uncached;
   } else {
      P->cpuStatus = cpu_running;
   }
   CHECK_LD_ANN(vAddr,pAddr);
   STATS_INC(P->myNum, dReads, 1);

   TraceUncachedDataRef(P, vAddr, pAddr);

   return ret;
}

/*****************************************************************
 *
 ****************************************************************/
void
MipsyNakUncachedOp(int cpuNum)
{
   CPUState *P = &PE[cpuNum];
   StatusReg statusReg;

   MipsyUnstall(cpuNum);
   statusReg.ts_data = P->CP0[C0_SR];
   if (statusReg.s32.ts_erl) {
      if (P->nPC == CACHE_ERR_VEC_BEV0) {
      /* HACK
         assume CPU was waiting for this uncached op to finish before
         starting the cache error handler, so make it take the error now.
         Undo effects of previous call to MipsyCacheError and call it again
         (this time with cpu_running) */
         CPUWarning("Uncached op nak'd on cpu %d while waiting for cache error\n",
                    cpuNum);
         P->nPC = P->CP0[C0_ERROR_EPC];
         MipsyCacheError(cpuNum, 1);
      }
   }
}

/*****************************************************************
 *
 *****************************************************************/
void
MipsyErrUncachedOp(int cpuNum, uint addr)
{
   CPUState *P = &PE[cpuNum];
   StatusReg statusReg;

   MipsyTakeBusError(cpuNum, FALSE, addr);

   /* dont need MipsyUnstall(cpuNum) because TakeBusError already does that */
   statusReg.ts_data = P->CP0[C0_SR];
   if (statusReg.s32.ts_erl) {
      if (P->nPC == CACHE_ERR_VEC_BEV0) {
      /* HACK
         assume CPU was waiting for this uncached op to finish before
         starting the cache error handler, so make it take the error now.
         Undo effects of previous call to MipsyCacheError and call it again
         (this time with cpu_running) */
         CPUWarning("Uncached op err'd on cpu %d while waiting for cache error\n",
                    cpuNum);
         P->nPC = P->CP0[C0_ERROR_EPC];
         MipsyCacheError(cpuNum, 1);
      }
   }
}

void
MipsyReissueUncachedOp(int cpuNum)
{
   MipsyUnstall(cpuNum);
}

void 
MipsyTurnOnCaches(void)
{
   mipsySkipCaches = FALSE;
}

void
MipsyTurnOffCaches(void)
{
   CPUWarning("MIPSY: Turning off caches without flushing.\n");
   mipsySkipCaches = TRUE;
}

bool
MipsyCachesAreOn(void)
{
   return !mipsySkipCaches;
}

/*****************************************************************
 * Bus errors that aren't determined until you are in the memory 
 * system will come back through this path
 *****************************************************************/
void
MipsyTakeBusError(int cpuNum, bool isIRef, VA vAddr)
{
   CPUState *P = &PE[cpuNum];
   PA pAddr;

   ASSERT((P->cpuStatus == cpu_stalled) || (P->cpuStatus == cpu_stalled_uncached));
   P->cpuStatus = cpu_running;

   if (TranslateVirtualNoSideeffect(P, vAddr, &pAddr) != SUCCESS) {
      CPUWarning("Couldn't translate virtual in MipsyTakeBusError\n");
      ASSERT(0);
   }

   MemRefRemoveReq(cpuNum, pAddr, SCACHE_LINE_SIZE);

   if (isIRef) {
      RECORD_EXCEPTION(P, EXC_IBE, E_VEC, vAddr, 
                       P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
   } else {
      RECORD_EXCEPTION(P, EXC_DBE, E_VEC, vAddr, 
                       P->CP0[C0_TLBHI], P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
   }
}

/*****************************************************************
 * MipsyRun
 * 
 * This is the interface into starting the fetch-decode-execute
 * loop. 
 *****************************************************************/
void 
MipsyRun(int swtch)
{
   int i;
   PrintRealTime("Simulation Start");

   MipsyInitFPU();
#ifdef MIPSY_MXS
   if ((mxsRunInterval > 0) && (mipsyRunInterval > 0)) {
       /* Run first in mipsy and then switch */
      EventDoCallback(0,SwitchSimulators, &switchSimHdr, 0, mipsyRunInterval);
   } else {
      int cpu;

       /* If we aren't going to switch back and forth, start in MXS */
      for (cpu=0; cpu < TOTAL_CPUS; cpu++)
         PE[cpu].inMXS = 1;
   }
#endif 

#ifdef T5_MODEL
   {
      int usingT5 = 0;
      ParamLookup(&usingT5, "MEMSYS.FLASH.UseNewtT5", PARAM_INT);
      if (usingT5) {
        ParamLookup(&T5NodeNum, "MEMSYS.FLASH.VerilogNodeNum", PARAM_INT);
      } else {
         T5NodeNum = -1;         /* Won't match any node numbers */
      }
   }
#endif      

   for (i=0; i < TOTAL_CPUS; i++) {
      /* Optimization to avoid directly indexing the PE array */
      pePtr[i] = &PE[i];
   }

   AnnFMInit(128);
   if (!swtch) {
      /* this is not a switch from another simulator */
      AnnCommonSetup();
      for (i=0; i < TOTAL_CPUS; i++) {
         P = &PE[i];
         AnnExec(AnnFind("simos", "enter"));
      }
   }

   /* Now jump into the main loop.When it is time for mipsy to quit */
   /* simulating, a longjmp will switch control here and then to */
   /* DoneRunning(). */ 

   if (setjmp(jmpEnv) != 0) {
      DoneRunning();
   } else {
      TraceInit();
      CPURun(NULL);
   }

#ifdef MIPSY_MXS
   if ((mxsRunInterval > 0) && (mipsyRunInterval > 0)) {
       EventCallbackRemove(&switchSimHdr);  
   }
#endif /* MIPSY_MXS */

   MemRefExit();

#ifdef DATA_HANDLING
#ifndef SOLO
   /* flush cache. This is inappropriate for SOLO, not to mention it crashes*/
   {
      int cpu;
      for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {
         FlushEntireCache(cpu, 0);
      }
   }
#endif
#endif
}

/****************************************************************
 * CPURun
 *
 * This is the fetch-decode-execute loop. Loop exit points include
 * exceptions and calls to the memory system to fetch instructions and
 * data. The premise behind exceptions is that the PC will not be 
 * incremented so that the exception handler can set the correct PC.
 * It takes the void * parameter to match the function type that
 * sproc() expects.
 ****************************************************************/
static void 
CPURun(void *Nada)
{
   register  CPUState *lastP; 
   register  CPUState *firstP;
   int i;

   firstP = &PE[0];
   lastP  = &PE[TOTAL_CPUS-1];
   P      = lastP;

   for (i=0; i < TOTAL_CPUS; i++) {
      P = &PE[i];
      pePtr[i] = &PE[i];
   }

   while (1) {
      Inst instr;
      register uint cpuNum;
      register uint op; 

      P++;

      if (P > lastP) {
         P = firstP;
         mipsyCurrentTime++; 
         EventPollSingleQueue(MipsyReadTime(0));
      } 
      
      if (P->cpuStatus != cpu_running) {
         /* 
          * A cpu can be halted or stalled. In solo mipsy, all but the 
          * first cpu is halted until the CREATE macro is encountered. 
          */ 
         continue;
      }

#ifdef USE_FLASHLITE
#ifdef SOLO
      if (sys_place_range_StallCPUS) {
         continue;
      }
#endif

#ifdef T5_MODEL
      /* 
       * If we're using the T5 model on this node to model the processor,
       * we'll need to make sure this node just idles 
       */
      if (T5NodeNum == P->myNum) {
         if (T5NodeNum == 0) {
            /* 
             * Special case for verilog on node 0: need to make sure 
             * Flashlite's threads can run as needed 
             */
            (void)  FlashAdvanceTime(MipsyReadTime(cpuNum));  
         }
         continue;
      }
#endif
#endif

      cpuNum = P->myNum;

      if (P->takeInterrupt) {
         if (P->stalledInst) {
         /* 
          * If we've reached this point, it means that we have just
          * unstalled the processor and are immediately supposed to
          * take an interrupt. In the past, this would smash the
          * current instruction and have it reissued when the
          * interrupt handling finished. Now we will first let the
          * unstall complete. This is especially useful in the
          * uncached cases where we don't want to reissue the ops.
          */
         } else {
            P->takeInterrupt = FALSE;
            if (!IN_MXS(P)) {
               EXCEPTION(P, EXC_INT);
            }
         }
      }

#ifdef MIPSY_MXS
      if (P->inMXS) {
        mxs:
         ms_cycle_once (P->st);
         continue;
      } else {
         if (P->switchToMXS && (P->PC == P->nPC-4) && (P->stalledInst == 0)) {
            P->inMXS = 1;
            P->switchToMXS = 0;
            CopyToMXS(P);
            CPUWarning("MXS: Switching to MXS on CPU%d at 0x%x time %lld\n", 
                       cpuNum, P->PC, (uint64)MipsyReadTime(cpuNum));
            goto mxs;
         }
      }
#endif

      /* 
       * Shortcut to keep from going through ReadInstruction again
       * after an instruction caused a dcache miss and stalled. When
       * the processor's data cache miss completes, we'll still have 
       * the instruction ready and waiting. 
       */

      if (P->stalledInst) {
         instr = P->stalledInst;
         P->stalledInst = FALSE;
      }  else { 
         Result ret;
         VA vAddr = P->PC;

         /* 
          * Anything we can do to avoid translating the virtual
          * address is a good thing. This is a quick check to see if
          * the current instruction is on the same page as the last
          * one. If so, we don't have to translate it again. This 
          * cache entry is of course cleared whenever there is a
          * chance that this translation is no longer correct. 
          */

         if (PAGE_NUMBER(vAddr) == P->pcVPNcache) {
            PA p = P->pcPaddrcache + PAGE_OFFSET(vAddr);

            if (SKIP_CACHES(P)) {
               instr = *(Inst *)HOST_DATA_ADDR(vAddr, p, cpuNum);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "sfetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(instr));
            } else {
               /* 
                * Do a quick check if this was in the last line 
                * checked. This cached address is set on a icache hit and 
                * is invalidated whenever a line is flushed from the 
                * icache. This could be changed to selectively delete the 
                * line, but these are infrequent actions. 
                */
               
               if (QUICK_ICACHE_CHECK(p, P)) {
                  int lineIndex;
                  /* 
                   * Quick cache hit! Be careful here - it won't work 
                   * with bypassing l1 caches right now. Don't need to 
                   * touch the lru bit since it will be set to this line. 
                   */
                  MS_INSTRUCTION_SET(P->myNum, P->cachedSetIndex);
                  MS_INSTRUCTION(cpuNum, p);
                  lineIndex = p & (ICACHE_LINE_SIZE-1);
                  instr = *(Inst *) (P->cachedILineData + lineIndex);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "qfetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(instr));
               } else {
                  /* 
                   * 2nd quickest route to the icache, no translation 
                   * needed, but we must check the cache. 
                   */
                  ret = MemRefReadInst(cpuNum, vAddr, p, &instr);
if (getenv("SIMOS_TRACEPC")) fprintf(stderr, "xfetch 0x%08x   0x%08x\r\n", (int)vAddr,BE2HO_4(instr));
                  if (ret != SUCCESS) {
                     if ((ret == STALL) || (ret == FAILURE)) {
                        P->stalledInst = 0;
                        STATS_SET(cpuNum, stallStart, MipsyReadTime(cpuNum));
                        P->cpuStatus = cpu_stalled;
                        continue;
                     } else if (ret == BUSERROR) {
                        RECORD_EXCEPTION(P, EXC_IBE, E_VEC, vAddr, P->CP0[C0_TLBHI], 
                                         P->CP0[C0_CTXT], P->CP0[C0_XCTXT]);
                     } else {
                        CPUError("Bad return(%d) from ReadICache\n", ret);
                     }
                  }
               }
            }
         } else { 
            /* 
             * This is the slow path to get an instruction. Full address 
             * translation and checking of the Icache is required. 
             */ 
            ret = ReadInstruction(vAddr, &instr);
            if (ret != SUCCESS) {
               if (P->cpuStatus != cpu_running) {
                  STATS_SET(cpuNum, stallStart, MipsyReadTime(cpuNum));
               }
               continue;
            } else {
               STATS_ADD_INTERVAL(cpuNum, stallTime, stallStart);
            }
         }

         /* 
          * The stalledInstr is stored in HO. In all other cases, we
          * instruction is fetched in BE and must be converted to HO.
          */
         instr = BE2HO_4(instr);

         STATS_INC(cpuNum, iReads, 1);
      };

      if (mipsy_debug_mode) {
	 if (mipsy_debug_mode > 1) {
	     mipsy_debug_mode--;
         } else if ((cpuNum == mipsy_break_nexti) 
             || (mipsy_break_nexti == MIPSY_BREAKANYCPU)) {
            /* 
             * MipsyDebug returns nonzero if the PC has changed 
             * or the contents of it have been overwritten, so it 
             * needs to be reloaded. 
             */
            if (MipsyDebug(cpuNum, 1)) {
               continue;
            }
         } else if (mipsy_sigusr) {
            mipsy_debug_mode = 0;
            mipsy_sigusr = 0;
            AnnExec(AnnFind("simos", "sigusr"));
         }
      }

      op = MAJOR_OP(instr);

      if (mipsOpcodes[op].func(instr, P) == SUCCESS) {
         /* CPUPrint("PC %llx - %s\n", P->PC, mipsOpcodes[op].opname);
          */
         /* Things to do after every successful instruction */
         FIX_REG_ZERO;
         INSTRUCTION_DONE_EVENT();

         if (RunPCAnnotations(P->PC, P->nPC)) 
            continue;
         P->PC = P->nPC;

         if (P->branchStatus == BranchStatus_taken) {
            P->nPC = P->branchTarget;
         } else {
            P->nPC += INST_SIZE;
         }

         if (P->branchStatus == BranchStatus_taken 
             || P->branchStatus == BranchStatus_nottaken ) { 
            P->branchStatus = BranchStatus_bd;
         } else { 
            P->branchStatus = BranchStatus_none;
         }
      }
   }
}

/*****************************************************************
 * DoneRunning
 *****************************************************************/
static void
DoneRunning(void) 
{
   PrintRealTime("Simulation End");
   MipsyExitFPU();

   /*
    * Mark as much true sharing as possible
    */
   FalseSharingCleanup();
   
   if (SKIP_CACHES(P)) {
      CPUWarning("DoneRunning and no caches being used\n");
   } else {
      if (mipsySyncWhenDone) {
         Result allret, ret;
         int timeout, i;
         CPUPrint("Syncing all processors at time %lld\n", (uint64) MipsyReadTime(0));
         for (timeout = 0; timeout < 1000*1000; timeout++) { 
            allret = SUCCESS;
            for (i = 0; i < TOTAL_CPUS; i++) {
               if (PE[i].cpuStatus == cpu_running) {
                  ret = MemRefSync(i);
                  if (ret == STALL) {
                     allret = ret;
                  }
               } else {
                  if (PE[i].cpuStatus != cpu_halted &&
                      PE[i].cpuStatus != cpu_idle) {
                     allret = STALL;
                  }
               }
            }
            if (allret == SUCCESS) 
               break;
            MIPSY_ADD_TIME(0, 1);
            EventPollSingleQueue(MipsyReadTime(0));
         } 
         if (allret != SUCCESS) 
            CPUWarning("Sync failed!\n"); 
      }
   }
}


/*****************************************************************
 * Mipsy-specific annotation code
 *****************************************************************/
void
MipsyInstallMemAnnotation(VA vAddr)
{
   /* Think of a clever way to optimize this! */
}

/*****************************************************************
 * MipsyTclInit - mipsy-specific tcl/memstat initialization
*****************************************************************/
extern int memstatOption;
#define MemStatNone 0
#define MemStatGlobal 1

void MipsyTclInit(Tcl_Interp *interp)
{
   Tcl_CreateCommand(interp, "instDump", PrintInstTclCmd,
                     (ClientData)NULL, (Tcl_CmdDeleteProc*)NULL);
   Tcl_CreateCommand(interp, "printInsts", PrintInstTclCmd,
                     (ClientData)NULL, (Tcl_CmdDeleteProc*)NULL);

#ifdef DASH_PREFETCH
   Tcl_CreateCommand(interp, "dashPrefetch", DashTclCmd,
                     (ClientData)NULL, (Tcl_CmdDeleteProc*)NULL);
#endif
   Tcl_CreateCommand(interp, "verboseDebug", InterpretVerboseDebug,
                     (char *)NULL, (Tcl_CmdDeleteProc*)NULL);
#ifdef TRACING
   Tcl_CreateCommand(interp, "traceDump", TraceDumpTclCmd,
                     (ClientData)NULL, (Tcl_CmdDeleteProc*)NULL);
#endif

   Tcl_LinkVar(interp, SaveString("SIMOS(SOLO)"), (char*)&isSolo,
               TCL_LINK_READ_ONLY | TCL_LINK_BOOLEAN);

   ParamRegister("PARAM(CPU.Mipsy.MipsySampleCycles)", (char *)&mipsyRunInterval, 
                 PARAM_INT);
   ParamRegister("PARAM(CPU.Mipsy.MXSSampleCycles)", (char *)&mxsRunInterval, 
                 PARAM_INT);
#ifdef SOLO
   memstatOption = MemStatNone;
#else
   memstatOption = MemStatGlobal;
#endif

#ifdef MIPSY_MXS
   ms_events_init();
#endif
}

/*****************************************************************
 * Tcl interface for controlling mipsy's vebose debugging
 *****************************************************************/
int 
InterpretVerboseDebug(ClientData clientData, Tcl_Interp *interp, int argc, char *argv[])
{

#ifndef DEBUG_DATA_VERBOSE
   Tcl_AppendResult(interp, 
                    "verboseDebug not supported unless mipsy compiled -DDEBUG_DATA_VERBOSE",
                    NULL);
   return TCL_ERROR;

#else 

#ifndef SOLO
   if (simosCPUType != MIPSY) {
      Tcl_AppendResult(interp, "verboseDebug not supported unless running in mipsy",
                       NULL);
      return TCL_ERROR;
   }
#endif
   if (argc < 2) {
      Tcl_AppendResult(interp, 
                       "Bad: should be: verboseDebug <on|off>", 
                       NULL);
      return TCL_ERROR;
   }

   if (!strcmp(argv[1], "off")) {
      CPUWarning("verboseDebug: Turning verbose cache debugging OFF\n");
      verboseDebugEnabled = 0;
   } else if (!strcmp(argv[1], "on")) {
      CPUWarning("verboseDebug: Turning verbose cache debugging ON\n");
      verboseDebugEnabled = 1;
   } else {
      Tcl_AppendResult(interp, 
                    "bad: should be: verboseDebug <on|off>", NULL);
      return TCL_ERROR;
   }

   return TCL_OK;
#endif
}


void 
MXSSwitch(int cpu, int enterMXS)
{
#ifdef MIPSY_MXS
   if ((PE[cpu].inMXS && enterMXS) || (!PE[cpu].inMXS && !enterMXS))
      return;
   if (enterMXS)
      PE[cpu].switchToMXS = 1;
   else
      PE[cpu].switchToMIPSY = 1;
   return;
#else
   CPUWarning("Trying to switch between mipsy and MXS, "
              "but this simos was built without MXS\n");
#endif
}

#ifdef MIPSY_MXS
/*
 * DoUncachedRead - perform an uncached/bdoor read for MXS.
 */
int 
DoUncachedRead(struct s_cpu_state *st, uint vAddr, uint pAddr, 
               int size, void *data)
{
   RefSize refsize;

   switch (size) {
   case 1: 
      refsize = BYTE_SZ; 
      break;
   case 2: 
      refsize = HALF_SZ; 
      break;
   case 4: 
      refsize = WORD_SZ; 
      break;
   case 8: 
      refsize = DOUBLE_SZ; 
      break;
   default: 
      ASSERT(0);
   }
   return MipsyReadMem(vAddr, data, refsize, NO_FLAVOR);
}

/*
 * DoUncachedWrite - perform an uncached/bdoor write for MXS
 */
int 
DoUncachedWrite(struct s_cpu_state *st,  uint vAddr, uint pAddr,  
                int size, int accel, void *data)
{
   RefSize refsize;

   switch (size) {
   case 1: 
      refsize = BYTE_SZ; 
      break;
   case 2: 
      refsize = HALF_SZ; 
      break;
   case 4: 
      refsize = WORD_SZ; 
      break;
   case 8: 
      refsize = DOUBLE_SZ; 
      break;
   default: 
      ASSERT(0);
   }
   return MipsyWriteMem(vAddr, data, refsize, NO_FLAVOR);
}


/*
 * GetLastException - Return the exception number of the last 
 *                    execption RECORDed by the RECORD_EXCEPTION macro.
 */

int
GetLastException(struct s_cpu_state *st)
{
   CPUState *P = (CPUState *) (st->mipsyPtr);
   return P->lastException;
}

void
RecordMxsMemsysStall(struct s_cpu_state *st, SimTime stallTime)
{
  CPUState *P = (CPUState *) (st->mipsyPtr);
  int cpuNum = P->myNum;

  STATS_INC(cpuNum, stallTime, stallTime);
}

static void 
SwitchSimulators(int cpuNum,EventCallbackHdr *hdr, void *arg)
{
   int i;
   SimTime interval;
   ASSERT( cpuNum ==  0 );
   if (PE[0].inMXS) {
      for (i = 0; i < TOTAL_CPUS; i++) {
         MXSSwitch(i,FALSE);
         /* WARNING - need switch simulators annotation */
      }
      interval = mipsyRunInterval;
   } else {
      for (i = 0; i < TOTAL_CPUS; i++) {
         MXSSwitch(i,TRUE);
         /* WARNING - need switch simulators annotation */       
      }
      interval = mxsRunInterval;
   }
   EventDoCallback(cpuNum, SwitchSimulators, &switchSimHdr, 0, interval);
}
#endif  /* MIPSY_MXS */