cpu.h
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/*
* Copyright (C) 1996-1998 by the Board of Trustees
* of Leland Stanford Junior University.
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
/*****************************************************************
* cpu.h
*
* Definitions and extraction macros for a MIPS Rx000 simulator.
*
* Author: $Author: blythe $
* Date: $Date: 2002/05/29 01:09:10 $
****************************************************************/
#ifndef MIPSY_CPU_H
#define MIPSY_CPU_H
#ifdef i386
#undef FS
#endif
/* CPU Global Functions */
extern void MipsyStall(int cpuNum);
extern void MipsyUnstall(int cpuNum);
extern SimTime MipsyCycleCount(int cpuNum);
extern SimTime MipsyCurrentCpuCycleCount(void);
extern SimTime MipsyInstructionCount(int cpuNum);
extern Result SyncMemsys(int cpuNum);
extern int MipsyCurrentCpuNum(void);
extern void MipsyTakeBusError(int cpuNum, bool isIRef, VA vAddr);
extern void MipsyInstallMemAnnotation(VA vAddr);
extern void MipsyTurnOnCaches(void);
extern void MipsyTurnOffCaches(void);
extern bool MipsyCachesAreOn(void);
extern void MipsyClearLockFlag(int);
extern bool MipsyGetLockFlag(int);
extern PA MipsyGetLockAddr(int);
#ifdef USE_MEMREF
#define UNCACHED_LL_SC 1
#else
#define UNCACHED_LL_SC (mipsySkipCaches)
#endif
#define SKIP_CACHES(_p) (mipsySkipCaches)
/* CPU Global Variables */
extern bool mipsyExit;
extern bool mipsySkipCaches;
/* CPU Global Constants */
#define INST_SIZE 4
#define CHECK_FOR_INTERRUPTS_INTERVAL 256
#define FIX_REG_ZERO (P->R[REG_ZERO] = 0)
#define SIGN_BIT32(_x) ((Reg32)(_x) & 0x80000000)
#define SIGN_BIT64(_x) ((Reg64)(_x) & 0x8000000000000000LL)
#if defined(SIM_MIPS32)
#define SIGN_BIT(_x) SIGN_BIT32(_x)
#define SIGN_EXTEND(_no, _val) SIGN_EXTEND32(_no,_val)
#else
#define SIGN_BIT(_x) SIGN_BIT64(_x)
#define SIGN_EXTEND(_no, _val) SIGN_EXTEND64(_no,_val)
#endif
#define SIGN_EXTEND32(_no, _val) ((((Reg32_s)(_val))<<(32-(_no)))>>(32-(_no)))
#define SIGN_EXTEND64(_no, _val) ((((Reg64_s)(_val))<<(64-(_no)))>>(64-(_no)))
#define ARITH_OVFL32(_res,_op1,_op2) (SIGN_BIT32(_op1) == SIGN_BIT32(_op2) \
&& SIGN_BIT32(_op1) != SIGN_BIT32(_res))
#define ARITH_OVFL64(_res,_op1,_op2) (SIGN_BIT64(_op1) == SIGN_BIT64(_op2) \
&& SIGN_BIT64(_op1) != SIGN_BIT64(_res))
#define TARGET_CACHE(_x) (((_x) & 0x00030000) >> 16)
#define CACHE_OP(_x) (((_x) & 0x001c0000) >> 16)
/* 'Cache' op related definitions */
/* Target cache */
#define CACH_PI 0x0 /* specifies primary inst. cache */
#define CACH_PD 0x1 /* primary data cache */
#define CACH_SI 0x2 /* secondary instruction cache */
#define CACH_SD 0x3 /* secondary data cache */
/* Cache operations */
#define C_IINV 0x0 /* index invalidate (inst, 2nd inst) */
#define C_IWBINV 0x0 /* index writeback inval (d, sd) */
#define C_ILT 0x4 /* index load tag (all) */
#define C_IST 0x8 /* index store tag (all) */
#define C_CDX 0xc /* create dirty exclusive (d, sd) */
#define C_HINV 0x10 /* hit invalidate (all) */
#define C_HWBINV 0x14 /* hit writeback inv. (d, sd) */
#define C_FILL 0x14 /* fill (i) */
#define C_HWB 0x18 /* hit writeback (i, d, sd) */
#define C_HSV 0x1c /* hit set virt. (si, sd) */
/*****************************************************************
* This information comes from "MIPS RISC ARCHITECTURE" and is *
* found on page 3-1. *
* *
* All instructions are 32 bits and aligned on a word boundary. *
* The three instruction types are Immediate, Jump, and Register.*
*****************************************************************/
/* CPU Extraction macros */
#define MAJOR_OP(_inst) (((uint)_inst >> 26) & 0x3f )
#define RS(_inst) (((uint)_inst >> 21) & 0x1f )
#define RT(_inst) (((uint)_inst >> 16) & 0x1f )
#define RD(_inst) (((uint)_inst >> 11) & 0x1f )
#define SHAMT(_inst) (((uint)_inst >> 6) & 0x1f )
#define FUNC(_inst) ((uint)_inst & 0x3f )
#define IMMED(_inst) ((uint)_inst & 0xffff )
#define TARGET(_inst) ((uint)_inst & 0x03ffffff )
#define IS_FCMP(_inst) (((uint)_inst >> 3) & 0x3 )
/* FPU Extraction macros */
#define FORMAT(_inst) (((uint)_inst >> 21) & 0x1f )
#define FT(_inst) (((uint)_inst >> 16) & 0x1f )
#define FS(_inst) (((uint)_inst >> 11) & 0x1f )
#define FD(_inst) (((uint)_inst >> 6) & 0x1f )
#define TF(_inst) (((uint)_inst >> 16) & 0x1 )
#endif /* CPU_H */