/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/*****************************************************************
 * mips_arch.h
 *
 * Generic mips architecture definition intended to be shared among
 * simulators. Most of this is taken from sbd.h.
 * 
 * $Author: blythe $
 * $Date: 2003/02/19 01:49:41 $
 *****************************************************************/
#ifndef MIPS_ARCH_H
#define MIPS_ARCH_H

#ifndef _LANGUAGE_ASSEMBLY

/* Has uint, etc */
#include <sys/types.h>
#include "simtypes.h"


#ifdef i386
#undef SP
#endif

/* TLB index register */
typedef Reg32 IndexReg;

/* TLB random register */
typedef Reg32 RandomReg;


/* TLB context register */


#ifdef HOST_BIG_ENDIAN

typedef union tlb_ctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    unsigned notused;
    unsigned tc_ptebase:9; /* bits 21-31 of kernel pte window */
    unsigned tc_badvpn:19;    /* vpn of faulting ref (ro) */
    unsigned :4;
  }s32;
  struct {
    Reg64 tc_ptebase:41; /* bits 21-63 of kernel pte window */
    Reg64 tc_badvpn:19;    /* vpn of faulting ref (ro) */
    Reg64  :4;
  }s64;
} ContextReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_ctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    unsigned :4;
    unsigned tc_badvpn:19;    /* vpn of faulting ref (ro) */
    unsigned tc_ptebase:9; /* bits 21-31 of kernel pte window */
    unsigned notused;
  }s32;
  struct {
    Reg64 :4;
    Reg64 tc_badvpn:19;    /* vpn of faulting ref (ro) */
    Reg64 tc_ptebase:41; /* bits 21-63 of kernel pte window */
  }s64;
} ContextReg;
#endif

#if defined(sgi) && !defined(_COMPILER_VERSION)
/* The old IRIX 5.3 compilers can't handle the following bit field. */
#define BIG_BIT_FIELD_BROKEN
#endif

#ifdef HOST_BIG_ENDIAN

typedef union tlb_Xctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    Reg64 tc_ptebase:27; 
    Reg64 tc_region:2;   
#ifndef BIG_BIT_FIELD_BROKEN
    Reg64 tc_badvpn:31;    /* vpn of faulting ref (ro) */
#else
    Reg64 tc_badvpn_hi3:3;   
    Reg64 tc_badvpn_lo28:28;   /* Patch around SGI compiler bug */
#endif
    Reg64 :4;
  }s64;
} XContextReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_Xctxt {
  Reg64 tc_data;               /* efficient access */
  struct {
    Reg64 :4;
    Reg64 tc_badvpn:31;    /* vpn of faulting ref (ro) */
    Reg64 tc_region:2;   
    Reg64 tc_ptebase:27;
  }s64;
} XContextReg;
#endif


/* TLB cause Register */
/* typedef Reg CauseReg;*/

#ifdef HOST_BIG_ENDIAN
typedef union {
  Reg32 tc_data;
  struct {
    unsigned tc_bd:1;
    unsigned :1;
    unsigned tc_ce:2;           /* Coprocessor Error - which one */
    unsigned :12;
    unsigned tc_ip:8;           /* Interrupt Pending */
    unsigned :1;
    unsigned tc_exccode:5;      /* Exception code (Table 6-2)
                                   changing to 7 to use sbd's exceptions */
    unsigned :2;
  }s32;
} CauseReg;
#endif
#ifdef HOST_LITTLE_ENDIAN
typedef union {
  Reg32 tc_data;
   struct {
      unsigned :2;
      unsigned tc_exccode:5;      /* Exception code (Table 6-2)
                                     changing to 7 to use sbd's exceptions */
      unsigned :1;
      unsigned tc_ip:8;           /* Interrupt Pending */
      unsigned :12;
      unsigned tc_ce:2;           /* Coprocessor Error - which one */
      unsigned :1;
      unsigned tc_bd:1;
      /* -- */

   }s32;
} CauseReg;
#endif


/* 
 * TLB status register
 */

#ifdef HOST_BIG_ENDIAN

typedef union tlb_status {
  Reg32 ts_data;
  struct {
    unsigned ts_xx:1;           /* Enable MIPS IV opcodes (1 == enabled )*/
    unsigned ts_cu2:1;		/* Usability of coprocessor 2 (1 = usable) */
    unsigned ts_cu1:1;		/* Usability of coprocessor 1 (1 = usable) */
    unsigned ts_cu0:1;		/* Usability of coprocessor 0 (1 = usable) */
    unsigned ts_rp:1;           /* reduce power operation 0=full speed */  
    unsigned ts_fr:1;           /* enable additional fpt regs, 0=16 1=32 */   
    unsigned ts_re:1;           /* reverse endian mode, not currently used*/
    /* diagnostic status fields */
    unsigned ts_dszero:2;       /* Some zeroes in the DS field */
    unsigned ts_bev:1;		/* Location of TLB refill and gen. exception 
				   vectors (0 = normal; 1 = bootstrap) */
    unsigned ts_ts:1;		/* TLB shut-down has occurred. */
    unsigned ts_sr:1;           /* soft reset has occured */   
    unsigned ts_nmi:1;          /* R10000 - nmi occured */
    unsigned ts_ch:1;           /* hit or miss indication of caches */
    unsigned ts_ce:1;           /* ECC controling bit */   
    unsigned ts_de:1;           /*cache parity/ECC errors cause no exceptions*/
    /* end diagnostic status fields */
    unsigned ts_im:8;           /* Interrupt Mask */
    unsigned ts_kx:1;           /* 64 bit in kernel mode */
    unsigned ts_sx:1;           /* 64 bit in supervisor mode */  
    unsigned ts_ux:1;           /* 64 bit in user mode */
    unsigned ts_ksu:2;          /* mode 10=user 01=superv 00=kernel */
    unsigned ts_erl:1;          /* Error level 0=normal */
    unsigned ts_exl:1;          /* Exception level 0=normal */
    unsigned ts_ie:1;           /* interrupt enable 0=disable */
  }s32;
} StatusReg;
#endif


#ifdef HOST_LITTLE_ENDIAN
typedef union tlb_status {
  unsigned ts_data;
  struct {

    unsigned ts_ie:1;           /* interrupt enable 0=disable */
    unsigned ts_exl:1;          /* Exception level 0=normal */
    unsigned ts_erl:1;          /* Error level 0=normal */
    unsigned ts_ksu:2;          /* mode 10=user 01=superv 00=kernel */
    unsigned ts_ux:1;           /* 64 bit in user mode */
    unsigned ts_sx:1;           /* 64 bit in supervisor mode */  
    unsigned ts_kx:1;           /* 64 bit in kernel mode */
    unsigned ts_im:8;           /* Interrupt Mask */
    /* end diagnostic status fields */
    unsigned ts_de:1;           /*cache parity/ECC errors cause no exceptions*/
    unsigned ts_ce:1;           /* ECC controling bit */   
    unsigned ts_ch:1;           /* hit or miss indication of caches */
    unsigned ts_nmi:1;          /* R10000 - nmi occured */
    unsigned ts_sr:1;           /* soft reset has occured */   
    unsigned ts_ts:1;		/* TLB shut-down has occurred. */
    unsigned ts_bev:1;		/* Location of TLB refill and gen. exception 
				   vectors (0 = normal; 1 = bootstrap) */
    unsigned ts_dszero:2;       /* Some zeroes in the DS field */
    /* diagnostic status fields */
    unsigned ts_re:1;           /* reverse endian mode, not currently used*/
    unsigned ts_fr:1;           /* enable additional fpt regs, 0=16 1=32 */   
    unsigned ts_rp:1;           /* reduce power operation 0=full speed */  
    unsigned ts_cu0:1;		/* Usability of coprocessor 0 (1 = usable) */
    unsigned ts_cu1:1;		/* Usability of coprocessor 1 (1 = usable) */
    unsigned ts_cu2:1;		/* Usability of coprocessor 2 (1 = usable) */
    unsigned ts_xx:1;           /* Enable MIPS IV opcodes (1 == enabled )*/
     /*  ------ */
     
  }s32;
} StatusReg;


#endif


typedef Reg EntryHi;           /* Hi part of a TLB Entry */
typedef Reg EntryLo;           /* Lo part of a TLB Entry */
typedef Reg32 EntryPgMsk;        /* Page Mask part of TLB Entry */
typedef struct tlbEntry {       /* Improve caching by pairing these */
   EntryPgMsk PgMsk;
   EntryHi Hi;
   EntryLo Lo0;
   EntryLo Lo1;
} TLBEntry;


/* Zero the field and then or in what is given (with its extra bits chopped off) */
#define CAUSE_SET_EXC(_reg, _code)\
(((uint)(_reg) & (~CAUSE_EXCMASK)) | \
(((uint)(_code) & (CAUSE_EXCMASK>>CAUSE_EXCSHIFT)) << CAUSE_EXCSHIFT))
/* We need this version because the shifted code is passed to EXCEPTION */
#define CAUSE_SET_EXC_NOSHIFT(_reg, _code)\
(((uint)(_reg) & (~CAUSE_EXCMASK)) | ((uint)(_code) & CAUSE_EXCMASK) )
#define CAUSE_SET_CE(_reg, _ce) \
(((uint)(_reg) & (~CAUSE_CEMASK)) | \
(((uint)(_ce) & (CAUSE_CEMASK>>CAUSE_CESHIFT)) << CAUSE_CESHIFT))
#define CAUSE_SET_BD(_reg, _bd) (_bd ? ((_reg) | CAUSE_BD) : \
((_reg) & (~CAUSE_BD)) )


/* Physical Line Number */
typedef Reg32 PLN;

/* K0 Virtual Address */
typedef Reg K0A;

/* Virtual Line Number */
typedef Reg VLN;

/* Virtual Page Number */
typedef Reg VPN;

/* Physical Page Number */
typedef Reg32 PFN;

/* Address Space Identifier */
typedef uint ASID;

#endif /* _LANGUAGE_ASSEMBLY */


#define INST_SIZE    4
#if defined(SIM_MIPS32)
#define REG_SIZE     4
#else
#define REG_SIZE     8
#endif
#define DEFAULT_PAGESZ      4096

#define NUM_GP_REGS  32
#define NUM_CP0_REGS 32
#define NUM_FP_REGS  32
#define NUM_FC_REGS  32

/* This is the hardware clock interrupt and is used to set the correct */
/* bit in the status and cause register */ 
#define CLOCK_INTR_BIT   (1 << 4)

/*
 * The following macros can be used to break apart and join VA and PA
 * addresses.
 */

/* TLB entry manipulation macros */
#define GET_ASID(addr) (((EntryHi)(addr) & TLBHI_PIDMASK) >> TLBHI_PIDSHIFT)
#ifdef notdef
#define GET_VPN(addr)  (((EntryHi)(addr) & TLBHI_VPNMASK) >> TLBHI_VPNSHIFT)
#endif
#define GET_PFN(addr)  (((EntryLo)(addr) & TLBLO_PFNMASK) >> TLBLO_PFNSHIFT)
#define GET_IDX(_idxreg) (((IndexReg)(_idxreg) & TLBINX_INXMASK) >> TLBINX_INXSHIFT)
#define TLBHI2ADDR(_ent) (_ent & TLBHI_VPN2MASK)
#define TLBLO2ADDR(_ent) (GET_PFN(_ent) << NUM_OFFSET_BITS)

#define IS_GLOBAL_HI(_enHi) ((EntryHi)(_enHi) & TLBHI_G)
#define IS_GLOBAL_LO(_enLo) ((EntryLo)(_enLo) & TLBLO_G)
#define CONVERT_TO_VPN2(_addrpfn) ((_addrpfn) >> 1)
#define GET_VPN2(_enHi) (((EntryHi)(_enHi) & TLBHI_VPN2MASK) >> STATIC_VPN2SHIFT)

#define GET_REGION(_enHi) (((Reg_s)(_enHi) >> TLBHI_REGIONSHIFT) & 3)

#define IS_LO_0(_pfn) (!((_pfn) & 1))

#define IS_CACHEABLE(_enLo) !((((EntryLo)(_enLo) & TLBLO_CACHMASK) == TLBLO_UNCACHED) ||   \
                             (((EntryLo)(_enLo) & TLBLO_CACHMASK) == TLBLO_UNCACHED_ACCEL))
#ifdef oldR4000
#define IS_CACHEABLE(_enLo) (((EntryLo)(_enLo) & TLBLO_CACHMASK) != TLBLO_UNCACHED)
#endif

#define GET_CACHE_ALGOR(_enLo) (((EntryLo)(_enLo) & TLBLO_CACHMASK)>>TLBLO_CACHSHIFT)

#define IS_GLOBAL(_en) ((_en) & TLBLO_G)
#define IS_VALID(_en)  ((_en) & TLBLO_V)
#define IS_NC(_en)     ((_en) & TLBLO_N)
#define IS_DIRTY(_en)  ((_en) & TLBLO_D)

#define IS_VALID_AND_CACHEABLE(_en)   (((_en) & TLBLO_V) && !(IS_NC((_en))))

# define NUM_ASID_BITS (8)
#if defined(SIM_MIPS32)
# define NUM_VPN_BITS (20)          /* vAddrs */
#else
# define NUM_VPN2_BITS (VA_VALID_BITS-NUM_OFFSET_BITS)  /* vAddrs */
#endif
# define NUM_OFFSET_BITS (12)       /* eventually not static */

#define NUM_INSTR_BITS  (32)
#define INVALID_ASID    ((1 << NUM_ASID_BITS) + 1)

#define PAGE_OFFSET(_addr)       ((_addr)&((1 << NUM_OFFSET_BITS) - 1))
#define PAGE_NUMBER(_addr)       (((uint)(_addr)) >> NUM_OFFSET_BITS)
#define FORM_ADDR(_pfn, _offset) (((_pfn) << NUM_OFFSET_BITS) | (_offset))


/* Zero the offset and add page */
#define NEXT_PAGE(_addr)         ((((VA)_addr) & (VA)(~(DEFAULT_PAGESZ-1))) + DEFAULT_PAGESZ)

/* Macros to cons up instructions ( ConsInstruction<instruction_type>) */
#define CIi(opCode, rt, rs, immed) ((int)\
((opCode) << 26 | (rs) << 21 | (rt) << 16 | ((immed) & 0xffff ) ) )

#define CIs(funct, rd, rs, rt) ((int)\
(spec_op << 26 | (rs) << 21 | (rt) << 16 | (rd) << 11 | funct) )

/* General Purpose Registers */
#define REG_ZERO   0
#define REG_AT     1
#define REG_V0     2
#define REG_V1     3
#define REG_A0     4
#define REG_A1     5
#define REG_A2     6
#define REG_A3     7
#define REG_T0     8
#define REG_T1     9
#define REG_T2     10
#define REG_T3     11
#define REG_T4     12 
#define REG_T5     13
#define REG_T6     14
#define REG_T7     15
#define REG_S0     16
#define REG_S1     17
#define REG_S2     18
#define REG_S3     19
#define REG_S4     20
#define REG_S5     21
#define REG_S6     22
#define REG_S7     23
#define REG_T8     24
#define REG_T9     25
#define REG_K0     26
#define REG_K1     27
#define REG_GP     28
#define REG_SP     29
#define REG_FP     30
#define REG_S8     30
#define REG_RA     31
#define REG_PC     32
#define REG_NPC    33
#define REG_HI     34
#define REG_LO     35

#define REG_NONE   48

#define REG_TA0    REG_T4
#define REG_TA1    REG_T5
#define REG_TA2    REG_T6
#define REG_TA3    REG_T7

/* A regdef.h style register naming convention */
/* Zero Register */
#define G0 0

/* Assembler Register */
#define ATR 1

/* used for interger return and static link */
#define V0 2
#define V1 3

/* Argument Registers */
#define A0 4
#define A1 5
#define A2 6
#define A3 7

/* Temporary Registers */
#define T0 8
#define T1 9
#define T2 10
#define T3 11
#define T4 12 
#define T5 13
#define T6 14
#define T7 15

/* Saved Registers */
#define S0 16
#define S1 17
#define S2 18
#define S3 19
#define S4 20
#define S5 21
#define S6 22
#define S7 23

#define T8 24
#define T9 25

#define K0 26
#define K1 27
#define GP 28

#define SP 29	

#define S8 30
#define FP 30

#define RA 31


/* Cop 0 SR */
#define assC0_SR 12

/* Floating Point Coprocessor (1) registers */
/* Each FPR is the concatenation of two FGR's */

#define REG_FPR_0   BASE_FPR_OFFSET+0
#define REG_FPR_2   BASE_FPR_OFFSET+8
#define REG_FPR_4   BASE_FPR_OFFSET+16
#define REG_FPR_6   BASE_FPR_OFFSET+24
#define REG_FPR_8   BASE_FPR_OFFSET+32
#define REG_FPR_10  BASE_FPR_OFFSET+40
#define REG_FPR_12  BASE_FPR_OFFSET+48
#define REG_FPR_14  BASE_FPR_OFFSET+56
#define REG_FPR_16  BASE_FPR_OFFSET+64
#define REG_FPR_18  BASE_FPR_OFFSET+72
#define REG_FPR_20  BASE_FPR_OFFSET+80
#define REG_FPR_22  BASE_FPR_OFFSET+88
#define REG_FPR_24  BASE_FPR_OFFSET+96
#define REG_FPR_26  BASE_FPR_OFFSET+104
#define REG_FPR_28  BASE_FPR_OFFSET+112
#define REG_FPR_30  BASE_FPR_OFFSET+120

/****************************************/
/* FCR31 is the Control/Status Register */
/* FS bit         [24]                  */
/* Condition bit  [23]                  */
/* Cause          [17:12]               */
/* Enables        [11:7]                */
/* Flags          [6:2]                 */
/* Rounding Mode  [1:0]                 */
/*           (Page 7-6)                 */
/****************************************/

#define ROUND_TO_NEAREST	0
#define ROUND_TO_ZERO		1
#define ROUND_TO_PLUS_INFINITY	2
#define ROUND_TO_MINUS_INFINITY	3

#define FPCSR_FLUSH_ZERO	0x01000000
#define	FPCSR_UNIMP		0x00020000
#define	FPCSR_EXCEPTIONS	0x0003f000	/* all exceptions */
#define	FPCSR_ENABLES		0x00000f80
#define	FPCSR_FLAGS		0x0000007c

/************************************************/
/* FCR0 is the Implementation/Revision Register */
/* Implementation Number [15:8]                 */
/* Revision Number       [7:0]                  */
/*               (Page 7-11)                    */
/************************************************/

#define S_csr_c  23
#define M_csr_c  (1<<S_csr_c)

/*
 * Coprocessor 0 registers
 * Some of these are r4000 specific.
 */
#ifdef _LANGUAGE_ASSEMBLY
#define	C0_INX		$0
#define	C0_RAND		$1
#define	C0_TLBLO_0	$2
#define	C0_TLBLO_1	$3
#define	C0_CTXT		$4
#define	C0_PGMASK	$5		/* page mask */
#define	C0_TLBWIRED	$6		/* # wired entries in tlb */
   /* 7 is not used */
#define	C0_BADVADDR	$8
#define	C0_COUNT	$9		/* free-running counter */
#define	C0_TLBHI	$10
#define	C0_COMPARE	$11		/* counter comparison reg. */
#define	C0_SR		$12
#define	C0_CAUSE	$13
#define	C0_EPC		$14
#define	C0_PRID		$15		/* revision identifier */
#define	C0_CONFIG	$16		/* hardware configuration */
#define	C0_LLADDR	$17		/* load linked address */
#define	C0_WATCHLO	$18		/* watchpoint */
#define	C0_WATCHHI	$19		/* watchpoint */
#define C0_XCTXT        $20 
#define C0_FRAMEMASK    $21
#define C0_BRDIAG       $22
  /* 23 & 24 are not defined */
#define C0_PC           $25
#define	C0_ECC		$26		/* S-cache ECC and primary parity */
#define	C0_CACHE_ERR	$27		/* cache error status */
#define	C0_TAGLO	$28		/* cache operations */
#define	C0_TAGHI	$29		/* cache operations */
#define	C0_ERROR_EPC	$30		/* ECC error prg. counter */


# else	/* ! _LANGUAGE_ASSEMBLY */

#define	C0_INX		0
#define	C0_RAND		1
#define	C0_TLBLO_0	2
#define	C0_TLBLO_1	3
#define	C0_CTXT		4
#define	C0_PGMASK	5		/* page mask */
#define	C0_TLBWIRED	6		/* # wired entries in tlb */
   /* 7 is not used */
#define	C0_BADVADDR	8
#define	C0_COUNT	9		/* free-running counter */
#define	C0_TLBHI	10
#define	C0_COMPARE	11		/* counter comparison reg. */
#define	C0_SR		12
#define	C0_CAUSE	13
#define	C0_EPC		14
#define	C0_PRID		15		/* revision identifier */
#define	C0_CONFIG	16		/* hardware configuration */
#define	C0_LLADDR	17		/* load linked address */
#define	C0_WATCHLO	18		/* watchpoint */
#define	C0_WATCHHI	19		/* watchpoint */
#define C0_XCTXT        20 
#define C0_FRAMEMASK    21
#define C0_BRDIAG       22
  /* 23 & 24 are not defined */
#define C0_PC           25
#define	C0_ECC		26		/* S-cache ECC and primary parity */
#define	C0_CACHE_ERR	27		/* cache error status */
#define	C0_TAGLO	28		/* cache operations */
#define	C0_TAGHI	29		/* cache operations */
#define	C0_ERROR_EPC	30		/* ECC error prg. counter */

   /* C0_PRID values */
#define C0_IMPMASK      0xff00
#define C0_IMPSHIFT     8
#define C0_REVMASK      0xff
#define C0_MAJREVMASK   0xf0
#define C0_MAJREVSHIFT  4
#define C0_MINREVMASK   0xf
#define C0_PRID_ZEROS   0xffff0000

/* Target cache */
#define	CACH_PI		0x0	/* specifies primary inst. cache */
#define	CACH_PD		0x1	/* primary data cache */
#define	CACH_SI		0x2	/* secondary instruction cache */
#define	CACH_SD		0x3	/* secondary data cache */

/* Cache operations */
#define	C_IINV		0x0	/* index invalidate (inst, 2nd inst) */
#define	C_IWBINV	0x0	/* index writeback inval (d, sd) */
#define	C_ILT		0x4	/* index load tag (all) */
#define	C_IST		0x8	/* index store tag (all) */
#define	C_CDX		0xc	/* create dirty exclusive (d, sd) */
#define	C_HINV		0x10	/* hit invalidate (all) */
#define	C_HWBINV	0x14	/* hit writeback inv. (d, sd) */
#define	C_FILL		0x14	/* fill (i) */
#define C_BARRIER       0x14    /* cache barrier (i) R10000 */
#define	C_HWB		0x18	/* hit writeback (i, d, sd) */
#define	C_HSV		0x1c	/* hit set virt. (si, sd) */


#endif	/* _LANGUAGE_ASSEMBLY */


/*
 * TLB size constants
 */


#define NTLBENTRIES_R4000   48
#define NTLBENTRIES_R10000  64
#define MAX_NTLBENTRIES	64    /* Maximum size of TLB */

#define VA_VALID_BITS       44
#define PA_VALID_BITS       40

#ifdef oldR40000
#define VA_VALID_BITS       40
#define PA_VALID_BITS       36
#endif



#if defined(SIM_MIPS32)

#define TLBHI_VPN2MASK	     0xffffe000
#define TLBHI_FILLMASK       0xffffffff
#define TLBHI_REGIONMASK     0x80000000
#define TLBHI_REGIONSHIFT    31

#else


#define TLBHI_VPN2MASK     0xfffffffe000LL	/* 44bits on R10000 */
#define TLBHI_FILLMASK       0xc0000fffffffffffLL

#ifdef oldR4000
#define TLBHI_VPN2MASK      0xffffffe000LL	/* 40 bit virtual
                                                   address on r4000 */
#define TLBHI_FILLMASK       0xc00000ffffffffffLL
#endif

#define TLBHI_REGIONMASK    0xc000000000000000LL
#define TLBHI_REGIONSHIFT       62

#endif

#define TLBHI_VPN2SHIFT         13
#define TLBHI_PIDMASK		0xff
#define TLBHI_PIDSHIFT	        0
#define TLBHI_ZEROS            (0x1f<<8)


#define TLBHI_NPID		255		/* 255 to fit in 8 bits */
#define TLBHI_G                0x00001000      /* G bit in tlb hi */
#define STATIC_VPN2SHIFT       13              

#if defined(SIM_MIPS32)
#define TLBLO_PFNMASK		0x3fffffc0
#define TLBLO_UNCACHED_ATTR     0x0
#else

#define TLBLO_PFNMASK	       0x3ffffffc0LL     
#define TLBLO_UNCACHED_ATTR    0xc000000000000000LL
#ifdef oldR4000
#define TLBLO_PFNMASK	       0x3fffffc0
#define TLBLO_UNCACHED_ATTR    0x0LL
#endif
#endif

#define TLBLO_PFNSHIFT		6
#define TLBLO_CACHMASK		0x38		/* cache coherency algorithm */
#define TLBLO_CACHSHIFT	        3

#define CBIT_UNCACHED           2
#define CBIT_NONCOHERENT        3
#define CBIT_EXCLUSIVE          4
#define CBIT_EXCLUSIVE_WRITE    5
#define CBIT_UPDATE             6
#define CBIT_UNCACHED_ACCEL     7

#define TLBLO_UNCACHED	       (CBIT_UNCACHED<<TLBLO_CACHSHIFT)		/* not cached */
#define TLBLO_COHRNT_EXL       (CBIT_EXCLUSIVE<<TLBLO_CACHSHIFT)      /* coherent exclusive */
#define TLBLO_COHRNT_UPDTW     (CBIT_UPDATE<<TLBLO_CACHSHIFT)        /* coherent update on write */ 
#define TLBLO_EXLWR	       (CBIT_EXCLUSIVE_WRITE<<TLBLO_CACHSHIFT)	/* Exclusive write */
#define TLBLO_UNCACHED_ACCEL  (CBIT_UNCACHED_ACCEL<<TLBLO_CACHSHIFT)		/* not cached */

#define TLBLO_D		0x4		/* writeable */
#define TLBLO_V		0x2		/* valid bit */
#define TLBLO_G		0x1		/* global access bit */

#define TLBLO_ZEROS     ~(TLBLO_PFNMASK|TLBLO_G|TLBLO_V|TLBLO_D|TLBLO_CACHMASK|TLBLO_UNCACHED_ATTR)

#define TLBINX_INXMASK		0x3f
#define TLBINX_INXSHIFT	        0
#define TLBINX_ZEROS            0x7fffffc0

#define TLBRAND_RANDMASK	0x3f
#define TLBRAND_RANDSHIFT	0
#define TLBRAND_ZEROS           ~TLBRAND_RANDMASK

#define TLBWIRED_WIREDMASK	0x3f
#define TLBWIRED_ZEROS          ~TLBWIRED_WIREDMASK


#define TLBCTXT_VPNSHIFT	4
#define TLBCTXT_VPNMASK         0x7ffff0
#define TLBCTXT_BASESHIFT	23
#define TLBCTXT_ZEROS           0xf

#define TLBCTXT32_BASEMASK	0xff800000
#define TLBCTXT32_BASEBITS	9
#define TLBCTXT64_BASEMASK	0xffffffffff800000LL
#define TLBCTXT64_BASEBITS	41


#define TLBPGMASK_4K		(0x0 << 13)
#define TLBPGMASK_16K		(0x3 << 13)
#define TLBPGMASK_64K		(0xf << 13)
#define TLBPGMASK_256K		(0x3f << 13)
#define TLBPGMASK_1M		(0xff << 13)
#define TLBPGMASK_4M		(0x3ff << 13)
#define TLBPGMASK_16M		(0xfff << 13)
#define TLBPGMASK_NUMSIZES       7
#define TLBPGMASK_ZEROS         0xfe001fff

#define TLBFRAMESHIFT           18


#define CNFIG_IC_SHIFT          29  
#define CNFIG_DC_SHIFT          26
#define CNFIG_SS_SHIFT          16

/*
 * Interrupt enable bits
 * (NOTE: bits set to 1 enable the corresponding level interrupt)
 */
#define SR_IMASK	0x0000ff00	/* Interrupt mask */
#define SR_IMASK8	0x00000000	/* mask level 8 */
#define SR_IMASK7	0x00008000	/* mask level 7 */
#define SR_IMASK6	0x0000c000	/* mask level 6 */
#define SR_IMASK5	0x0000e000	/* mask level 5 */
#define SR_IMASK4	0x0000f000	/* mask level 4 */
#define SR_IMASK3	0x0000f800	/* mask level 3 */
#define SR_IMASK2	0x0000fc00	/* mask level 2 */
#define SR_IMASK1	0x0000fe00	/* mask level 1 */
#define SR_IMASK0	0x0000ff00	/* mask level 0 */

#define SR_IBIT8	0x00008000	/* bit level 8 */
#define SR_IBIT7	0x00004000	/* bit level 7 */
#define SR_IBIT6	0x00002000	/* bit level 6 */
#define SR_IBIT5	0x00001000	/* bit level 5 */
#define SR_IBIT4	0x00000800	/* bit level 4 */
#define SR_IBIT3	0x00000400	/* bit level 3 */
#define SR_IBIT2	0x00000200	/* bit level 2 */
#define SR_IBIT1	0x00000100	/* bit level 1 */

#define SR_CUMASK	0xf0000000	/* coproc usable bits */

#define SR_CU3		0x80000000	/* Coprocessor 3 usable */
#define SR_CU2		0x40000000	/* Coprocessor 2 usable */
#define SR_CU1		0x20000000	/* Coprocessor 1 usable */
#define SR_CU0		0x10000000	/* Coprocessor 0 usable */

#define SR_SR		0x00100000	/* soft reset occured */
#define SR_CH		0x00040000	/* Cache hit for last 'cache' op */
#define SR_CE		0x00020000	/* Create ECC */
#define SR_DE		0x00010000	/* ECC of parity does not cause error */
#define SR_RP		0x08000000	/* enable reduced-power operation */
#define SR_FR		0x04000000	/* enable additional fp registers */
#define SR_RE		0x02000000	/* reverse endian in user mode */

#define SR_KX		0x00000080	/* extended-addr TLB vec in kernel */
#define SR_SX		0x00000040	/* xtended-addr TLB vec supervisor */
#define SR_UX		0x00000020	/* xtended-addr TLB vec in user mode */
#define SR_KSU_MSK	0x00000018	/* 2 bit mode: 00b=>k, 10b=>u */
#define SR_KSU_USR	0x00000010	/* 2 bit mode: 00b=>k, 10b=>u */
#define SR_KSU_KS	0x00000008	/* 0-->kernel 1-->supervisor */
#define SR_KSU_SUP	SR_KSU_KS
#define SR_ERL		0x00000004	/* Error level, 1=>cache error */
#define SR_EXL		0x00000002	/* Exception level, 1=>exception */
#define SR_IE		0x00000001	/* interrupt enable, 1=>enable */
#define SR_IEC		SR_IE		/* compat with R3000 source */
#define SR_PREVMODE	SR_KSU_MSK	/* previous kernel/user mode */
#define SR_ZEROS        (3<<23)
/*
 * Cause Register
 */
#define	CAUSE_BD	0x80000000	/* Branch delay slot */
#define	CAUSE_CEMASK	0x30000000	/* coprocessor error */
#define	CAUSE_CESHIFT	28

/* Interrupt pending bits */
#define	CAUSE_IP8	0x00008000	/* Internal level 8 pending */
#define	CAUSE_IP7	0x00004000	/* External level 7 pending */
#define	CAUSE_IP6	0x00002000	/* External level 6 pending */
#define	CAUSE_IP5	0x00001000	/* External level 5 pending */
#define	CAUSE_IP4	0x00000800	/* External level 4 pending */
#define	CAUSE_IP3	0x00000400	/* External level 3 pending */
#define	CAUSE_SW2	0x00000200	/* Software level 2 pending */
#define	CAUSE_SW1	0x00000100	/* Software level 1 pending */

               /* Cause bits set by external interrupts */
#define CAUSE_EXTINTBITS   (CAUSE_IP7|CAUSE_IP6|CAUSE_IP5|CAUSE_IP4|CAUSE_IP3)

#define	CAUSE_IPMASK	0x0000FF00	/* Pending interrupt mask */
#define	CAUSE_IPSHIFT	8
#define	CAUSE_EXCMASK	0x0000007C	/* Cause code bits */

#define	CAUSE_EXCSHIFT	2

#define CAUSE_ZEROS     ((0x1<<30)|(0xfff<<16)|(1<<7)|0x3)

/* Cause register exception codes */
#define	EXC_CODE(x)	((x)<<2)

/* Hardware exception codes */
#define	EXC_INT		EXC_CODE(0)	/* interrupt */
#define	EXC_MOD		EXC_CODE(1)	/* TLB mod */
#define	EXC_RMISS	EXC_CODE(2)	/* Read TLB Miss */
#define	EXC_WMISS	EXC_CODE(3)	/* Write TLB Miss */
#define	EXC_RADE	EXC_CODE(4)	/* Read Address Error */
#define	EXC_WADE	EXC_CODE(5)	/* Write Address Error */
#define	EXC_IBE		EXC_CODE(6)	/* Instruction Bus Error */
#define	EXC_DBE		EXC_CODE(7)	/* Data Bus Error */
#define	EXC_SYSCALL	EXC_CODE(8)	/* SYSCALL */
#define	EXC_BREAK	EXC_CODE(9)	/* BREAKpoint */
#define	EXC_II		EXC_CODE(10)	/* Illegal Instruction */
#define	EXC_CPU		EXC_CODE(11)	/* CoProcessor Unusable */
#define	EXC_OV		EXC_CODE(12)	/* OVerflow */
#define EXC_TRAP	EXC_CODE(13)	/* Trap exception */
#define EXC_VCEI	EXC_CODE(14)	/* Virt. Coherency on Inst. fetch */
#define EXC_FPE	        EXC_CODE(15)	/* Floating Point Exception */
#define EXC_WATCH	EXC_CODE(23)	/* Watchpoint reference */
#define EXC_VCED	EXC_CODE(31)	/* Virt. Coherency on data read */

/* Write masks for CP0 registers. */
#ifndef _LANGUAGE_ASSEMBLY
typedef struct {
    int size;  /* 0 = 32bit, 1 = 64bit, -1 = notvalid */
    uint64 zero_mask;    /* bits must be zero */
    int read_only;                   /* non zer0 if read-only */
} Cp0RegControl;

#endif

#define CP0_REG_CONTROL_ARRAY { \
    {0, TLBINX_ZEROS, 0x0},            /* 0 - 32bit Index */   \
    {0, TLBRAND_RANDMASK, -1},         /* 1 - 32bit Random */  \
    {1, TLBLO_ZEROS, 0x0},             /* 2 - 64bit TLBLo0 */    \
    {1, TLBLO_ZEROS, 0x0},             /* 3 - 64bit TLBLo1 */    \
    {1, TLBCTXT_ZEROS, 0x0},           /* 4 - 64bit Context */   \
    {0, TLBPGMASK_ZEROS,0x0},          /* 5 - 32bit PageMask */  \
    {0, TLBWIRED_ZEROS,0x0},           /* 6 - 32bit wired */     \
    {-1,-1LL,0},                       /* 7 - notvalid */        \
    {1, 0x0,-1},                       /* 8 - 64bit badVaddr */  \
    {0, 0x0,0},                        /* 9 - 32bit count */     \
    {1,TLBHI_ZEROS, 0},                /* 10 - 64bit TLBHI */    \
    {0, 0x0,0},                        /* 11 - 32bit compare */  \
    {0, SR_ZEROS,0},                   /* 12 - 32bit status */   \
    {0, CAUSE_ZEROS,0},                /* 13 - 32bit cause */    \
    {1, 0,0},                          /* 14 - 64bit EPC */      \
    {0, C0_PRID_ZEROS, -1},            /* 15 - 32bit PRid reg */ \
    {0, 0, 0},              	       /* 16 - 32bit config reg */  \
    {0, 0, 0},                         /* 17 - 32bit LL reg */   \
    {0, 0, 0},                         /* 18 - 32bit watchLo */  \
    {0, 0xffffff00, 0},                /* 19 - 32bit watchHi */  \
    {1, 0xfLL, 0},                     /* 20 - 64bit xcontext */ \
    {0, 0xffff0000, 0},                /* 21 - 32bit framemask */ \
    {1, 0, -1},                        /* 22 - 64bit diag reg. */ \
    {-1, -1LL, 0},                     /* 23 - notvalid */        \
    {-1, -1LL, 0},                     /* 24 - notvalid */        \
    {0, 0xfffffe00, 0},                /* 25 - 32bit perf counter */ \
    {0, 0xfffffc00, 0},                /* 26 - 32bit ECC reg */    \
    {0, 0,0} ,                         /* 27 32bit cache reg */    \
    {0, 0,0} ,                         /* 28 32bit cache reg */    \
    {0, 0,0} ,                         /* 29 32bit cache reg */    \
    {1,0,0},                           /* 30, 64bit ErrorPC */     \
    {-1,0,0}}                          /* 31 -  not valid */      


/*
 * XXX I think that TORNADO is correct on this one
 * XXX should check that it is ok with IRIX and 
 * XXX remove the ifdef. bugnion
 */
#if defined(TORNADO) || defined(IRIX6_4)
#define COUNTER_FREQUENCY_DIVIDER 2
#else
#define COUNTER_FREQUENCY_DIVIDER 1
#endif



/* Instruction op codes */
/* major opcodes */
#define spec_op		0x00
#define bcond_op	0x01
#define j_op		0x02
#define jal_op		0x03

#define beq_op		0x04
#define bne_op		0x05
#define blez_op		0x06
#define bgtz_op		0x07

#define addi_op		0x08
#define addiu_op	0x09
#define slti_op		0x0A
#define sltiu_op	0x0B

#define andi_op		0x0C
#define ori_op		0x0D
#define xori_op		0x0E
#define lui_op		0x0F

#define cop0_op		0x10
#define cop1_op		0x11
#define cop2_op		0x12
#define cop1x_op        0x13

#define beql_op		0x14
#define bnel_op		0x15
#define blezl_op	0x16
#define bgtzl_op	0x17

#define daddi_op        0x18
#define daddiu_op       0x19
#define ldl_op          0x1A
#define ldr_op          0x1B

#define lb_op		0x20
#define lh_op		0x21
#define lwl_op		0x22
#define lw_op		0x23

#define lbu_op		0x24
#define lhu_op		0x25
#define lwr_op		0x26
#define lwu_op		0x27

#define sb_op		0x28
#define sh_op		0x29
#define swl_op		0x2A
#define sw_op		0x2B

#define sdl_op		0x2C
#define sdr_op		0x2D
#define swr_op		0x2E
#define cache_op	0x2F

#define ll_op		0x30
#define lwc1_op		0x31
#define lwc2_op		0x32
#define pref_op		0x33

#define lld_op		0x34
#define ldc1_op		0x35
#define ldc2_op		0x36
#define	ld_op		0x37

#define sc_op		0x38
#define swc1_op		0x39
#define swc2_op		0x3A

#define scd_op		0x3C
#define sdc1_op		0x3D
#define sdc2_op		0x3E
#define	sd_op		0x3F

/* func field of spec opcode */
#define sll_op		0x00
#define movc_op         0x01
#define srl_op		0x02
#define sra_op		0x03

#define sllv_op		0x04
#define srlv_op		0x06
#define srav_op		0x07

#define jr_op		0x08
#define jalr_op		0x09
#define movz_op         0x0A
#define movn_op         0x0B

#define syscall_op	0x0C
#define break_op	0x0D
#define spim_op		0x0E
#define sync_op		0x0F

#define mfhi_op		0x10
#define mthi_op		0x11
#define mflo_op		0x12
#define mtlo_op		0x13

#define dsllv_op	0x14
#define dsrlv_op	0x16
#define dsrav_op	0x17

#define mult_op		0x18
#define multu_op	0x19
#define div_op		0x1A
#define divu_op		0x1B

#define dmult_op	0x1C
#define dmultu_op	0x1D
#define ddiv_op		0x1E
#define ddivu_op	0x1F

#define add_op		0x20
#define addu_op		0x21
#define sub_op		0x22
#define subu_op		0x23

#define and_op		0x24
#define or_op		0x25
#define xor_op		0x26
#define nor_op		0x27

#define slt_op		0x2A
#define sltu_op		0x2B

#define dadd_op		0x2C
#define daddu_op	0x2D
#define dsub_op		0x2E
#define dsubu_op	0x2F

#define tge_op		0x30
#define tgeu_op		0x31
#define tlt_op		0x32
#define tltu_op		0x33

#define teq_op		0x34
#define tne_op		0x36

#define dsll_op         0x38
#define dsrl_op         0x3A
#define dsra_op         0x3B

#define dsll32_op       0x3C
#define dsrl32_op       0x3E
#define dsra32_op       0x3F

/* rt field of bcond opcodes */
#define bltz_op		0x00
#define bgez_op		0x01
#define bltzl_op	0x02
#define bgezl_op	0x03

#define spimi_op	0x04

#define tgei_op		0x08
#define tgeiu_op	0x09
#define tlti_op		0x0A
#define tltiu_op	0x0B

#define teqi_op		0x0C
#define tnei_op		0x0E

#define bltzal_op	0x10
#define bgezal_op	0x11
#define bltzall_op	0x12
#define bgezall_op	0x13

/* rs field of cop opcodes */
#define mfc_op		0x00
#define dmfc_op		0x01
#define cfc_op		0x02
#define mtc_op		0x04
#define dmtc_op		0x05
#define ctc_op		0x06
#define bc_op		0x08
#define cop_op		0x10
#define copd_op		0x11
#define copw_op		0x14
#define copl_op		0x15
#define copm_op         0x18

/* func field of cop0 COI opcodes */
#define tlbr_op		0x01
#define tlbwi_op	0x02
#define tlbwr_op	0x06
#define tlbp_op		0x08
#define rfe_op		0x10
#define eret_op		0x18

/* func field of cop0 COM opcodes */
#define tlbr1_op	0x01
#define tlbw_op         0x02
#define tlbp1_op	0x08
#define dctr_op         0x09
#define dctw_op         0x0A

/* fmt field of cop1 opcodes */
#define	s_fmt		0
#define	d_fmt		1
#define	e_fmt		2
#define q_fmt		3
#define	w_fmt		4
#define l_fmt		5

/* func field of cop1/{s,d,w} opcodes */
#define fadd_op		0x00
#define fsub_op		0x01
#define fmul_op		0x02
#define fdiv_op		0x03

#define fsqrt_op	0x04
#define fabs_op		0x05
#define fmov_op		0x06
#define fneg_op		0x07

#define froundl_op	0x08
#define ftruncl_op	0x09
#define fceill_op	0x0a
#define ffloorl_op	0x0b

#define fround_op	0x0c
#define ftrunc_op	0x0d
#define fceil_op	0x0e
#define ffloor_op	0x0f

#define fmovc_op        0x11
#define fmovz_op        0x12
#define fmovn_op        0x13

#define frecip_op       0x15
#define frsqrt_op       0x16

#define fcvts_op	0x20
#define fcvtd_op	0x21
#define fcvte_op	0x22

#define fcvtw_op	0x24
#define fcvtl_op	0x25

#define fcmp_op		0x30

/* func field of cop1x opcodes */

#define lwxc1_op        0x00
#define ldxc1_op        0x01
#define pfetch_op       0x07
#define swxc1_op        0x08
#define sdxc1_op        0x09
#define madd_s_op       0x20
#define madd_d_op       0x21
#define madd_e_op       0x22
#define msub_s_op       0x28
#define msub_d_op       0x29
#define msub_e_op       0x2a
#define nmadd_s_op      0x30
#define nmadd_d_op      0x31
#define nmadd_e_op      0x32
#define nmsub_s_op      0x38
#define nmsub_d_op      0x39
#define nmsub_e_op      0x3a

/* func field for mad opcodes (ma_format.func) */
#define madd_op         0x08
#define msub_op         0x0a
#define nmadd_op        0x0c
#define nmsub_op        0x0e

#endif /* MIPS_ARCH_H */