/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

 /*****************************************************************
 * simmagic.c
 *
 * Interface between the OS view of the machine and the SimOS
 * device simulators.
 *
 * Created by: John Chapin, 05/95
 * Revision history:
 *   06/95  (Dan Teodosiu) added interrupt subsystem support.
 *   06/95  (John Chapin)  added register access, interrupt event codes
 *   06/95  (John Chapin)  moved flash defines out, added universal I/O ops
 *   11/95  (John Chapin)  added PPC version 2 support
 *   07/96  (Dan Teodosiu) complete OS/SimOS overhaul
 *   02/97  (Ben Werther)  generalized number of devices per machine
 *
 ****************************************************************/

#include "sim.h"

#include <stdio.h>
#include <sys/types.h>
#include <sys/mman.h>
#include <sys/file.h>
#include <sys/signal.h>
#ifndef __alpha
#ifndef i386
#include <sys/unistd.h>
#include <sys/ioccom.h>
#include <sys/filio.h>
#include <netinet/in.h>
#endif
#endif
#include <sys/time.h>
#include <sys/uio.h>
#include <unistd.h>
#include <string.h>

#ifdef sgi
#include <netinet/if_ether.h>
#endif

#include <errno.h>
#include <netdb.h>
#include <stdlib.h>

#include "machine_defs.h"

#include "syslimits.h"
#include "simtypes.h"
#include "checkpoint.h"
#include "machine_params.h"
#include "cpu_interface.h"
#include "cpu_state.h"
#include "sim_error.h"
#include "addr_layout.h"
#include "registry.h"
#include "dma.h"
#include "../../devices/disk/simos_interface.h"
#include "remote_access.h"
#include "simutil.h"
#include "../../memsystems/flashlite/flash_interface.h"
#include "../../memsystems/memsys.h"

#include "simmisc.h"
#include "simmagic.h"
#include "hd.h"
#include "console.h"
#include "ethernet.h"
#include "startup.h"
#define BBPLAYER


extern void rcp_init(void);
static int BDOOR_RCP_access(int cpuNum, uint VA, int type, void* buf);
#if 0
static int BDOOR_PIF_access(int cpuNum, uint VA, int type, void* buf);
#endif
static int BDOOR_CD1_access(int cpuNum, uint VA, int type, void* buf);
static int BDOOR_RDB_access(int cpuNum, uint VA, int type, void* buf);
#ifdef BBPLAYER
static int BDOOR_SRAM_access(int cpuNum, uint VA, int type, void* buf);
static int BDOOR_VIRAGE_access(int cpuNum, uint VA, int type, void* buf);
#endif

/* Cache counting stuff. The routines are in numa.c */
#define IS_NUMA() (memsysVec.type == NUMA)
uint64 MigRepGetHotPage(int memnum);
uint64 MigRepGetInfo(unsigned long addr, int memnum, 
                                 unsigned long countType, unsigned long countAddr);
void MigRepSetInfo(unsigned long addr, int memnum, uint64 val,
                   unsigned long countType, unsigned long countAddr);

/* Control debugging info printout: 0=off, 1=on */
#define DEBUG_MAGIC 0

#define offsetof(t,m) ((int)&((t*)0)->m)

int FPromUseFL;

long initialBootTime; 

static CptCallback SimMagic_CheckpointCB;

typedef struct MagicStatus {

  MagicRegister iPendingReg;   /* 64b interrupt pending reg */
  MagicRegister iTransReg;     /* 64b int pending reg (transition-sensitive) */
  MagicRegister iEnableMask;   /* 64b interrupt enable mask */
  unsigned char iBitTable[64]; /* IEC -> CPU intrBits map
				* Note: read/written in 64-bit 
				* chunks so must be aligned
				*/
  MagicRegister IEChigh;       /* current interrupt level (board) */

  IEC           ioSlotMap[SIM_MAXSLOTS]; /* slot -> IEC map */
  IEC           ioSlots[SIM_MAXSLOTS];   /* pending count for each slot */
  
  int           timerInterval; /* 0 => no timer interrupt on this CPU
				* > 0 => interrupt with specified
				* periodicity [us].
				*/

  MagicRegister workerMask;    /* mask bits for cell boundary */
  MagicRegister workerMatch;   /* match bits for cell id */

} MagicStatus;

MagicStatus mm[SIM_MAXCPUS]; /* MAGIC status for all nodes */

DeviceToMachineStruct deviceToMachine; /* Device to machine mappings */

/*
 * Save someone a bunch of debugging time if they use some of SGI compilers
 * that doesn't sign-extend correctly when optimization is turned on.
 */
#define CHECK_FOR_COMPILER_BUG CheckForCompilerBug(0x80000000,(VA)0xffffffff80000000LL)
static void
CheckForCompilerBug(uint addr, VA val)
{
   VA   vAddr = (VA)(Reg32_s)addr; /* Sign extend if needed */
   if (vAddr != val) CPUError("Your compiler is broken\n");
}

#define CHECK_FOR_COMPILER_BUG2 \
  CheckForCompilerBug2(0x80000000,(Reg)0xffffffff80000000LL)

static void
CheckForCompilerBug2(Reg addr, Reg val)
{
   Reg new = (Reg)(Reg32_s)addr; /* Sign extend if needed */
   if (new != val) CPUWarning("CAREFUL: Your compiler is broken\n");
}

/****************************************************************************
 *
 * Interrupt subsystem
 *
 ****************************************************************************/

/* recompute intrBits for the specified CPU. */
void
recompute_intr_bits(register int cpu)
{
  MagicRegister pend;
  MagicRegister trans;
  int           iechigh;
  int i;
  MagicRegister mask;

  ASSERT(!USE_MAGIC());
  
  /* compute IEChigh = ffsb(pend) */
  pend = mm[cpu].iPendingReg & mm[cpu].iEnableMask;
  if (pend == 0) {
      iechigh = 0;
  } else {
    for (iechigh = -1; pend >= (1<<8); pend >>= 8) iechigh += 8;
    for ( ; pend != 0; pend >>= 1)                 iechigh++;
  }
  mm[cpu].IEChigh = iechigh;

  /* compute cause bits */
  trans = mm[cpu].iTransReg & mm[cpu].iEnableMask;
  CPUVec.intrBits[cpu] = 0;
  for(i=0, mask = 1; i < 64; i++, mask <<= 1) {
     if (trans & mask) CPUVec.intrBits[cpu] |= (mm[cpu].iBitTable[i]<<2);
  }

  CPUVec.IntrBitsChanged(cpu);
}

void
ChangeInterrupt(int cpu, int code, int v) {
    if (v)
        CPUVec.intrBits[cpu] |= code; 
    else
	CPUVec.intrBits[cpu] &= ~code;
    CPUVec.IntrBitsChanged(cpu);
}

void
RaiseIBit(int cpu, IEC code)
{
  MagicRegister ibit = ((MagicRegister)1) << code;

  ASSERT(!USE_MAGIC());

  if (!(mm[cpu].iPendingReg & ibit)) {
    /* 0->1 transition */
#if (DEBUG_MAGIC == 1)
    LogEntry("RaiseIBit", cpu, "code=0x%x 0->1 transition\n", code);
#endif
    mm[cpu].iPendingReg |= ibit;
    mm[cpu].iTransReg   |= ibit;
    recompute_intr_bits(cpu);
  } else {
    /* no transition */
#if (DEBUG_MAGIC == 1)
    LogEntry("RaiseIBit", cpu, "code=0x%x no transition\n", code);
#endif
  }
}

void
ClearIBit(int cpu, IEC code)
{
  MagicRegister ibit = ((MagicRegister)1) << code;

  ASSERT(!USE_MAGIC());

  if ((mm[cpu].iPendingReg & ibit)) {
    /* 1->0 transition */
#if (DEBUG_MAGIC == 1)
    LogEntry("ClearIBit", cpu, "code=0x%x 1->0 transition\n", code);
#endif
    mm[cpu].iPendingReg &= ~ibit;
    mm[cpu].iTransReg   &= ~ibit;
    recompute_intr_bits(cpu);
  } else {
    /* no transition */
#if (DEBUG_MAGIC == 1)
    LogEntry("ClearIBit", cpu, "code=0x%x no transition\n", code);
#endif
  }
}

static void
RaiseSlot(int cpu, int slot)
{
  ASSERT(0 <= cpu && cpu < TOTAL_CPUS);
  ASSERT(0 <= slot && slot < SIM_MAXSLOTS);
#if (DEBUG_MAGIC == 1)
  LogEntry("RaiseSlot",cpu,"slot=%d  prevVal=0x%x\n",
	   slot, mm[cpu].ioSlots[slot]);
#endif
  if (mm[cpu].ioSlots[slot]++ == 0) {
    /* Slot transitions 0->1, must raise interrupt bit */
    if (USE_MAGIC()) {
      FlashliteRaiseSlot(cpu, slot);
    } else {
      RaiseIBit(cpu, mm[cpu].ioSlotMap[slot]);
    }
  }
}


void
ClearSlot(int cpu, int slot)
{
  register int slotval;
  
  ASSERT(0 <= cpu && cpu < TOTAL_CPUS);
  ASSERT(0 <= slot && slot < SIM_MAXSLOTS);
#if (DEBUG_MAGIC == 1)
  LogEntry("ClearSlot",cpu,"slot=%d  prevVal=0x%x\n",
	   slot, mm[cpu].ioSlots[slot]);
#endif
  slotval = --mm[cpu].ioSlots[slot];
  if (slotval < 0) {
     /* this can occur if: console TX_INTR is
      * pending when a cell is rebooted.  This gets cleared once
      * during cell initialization and again on the next GetIntrStatus
      * since flags in the simulated console device are still set.
      */
      Sim_Warning("ClearSlot(%d, %d): slot value dropped below 0\n", 
                  cpu, slot);
      mm[cpu].ioSlots[slot] = 0;
  } else if (slotval == 0) {
    /* Slot transitions 1->0, must clear interrupt bit. */
    if (USE_MAGIC()) {
      FlashliteClearSlot(cpu, slot);
    } else { 
      ClearIBit(cpu, mm[cpu].ioSlotMap[slot]);
    }
  }
}


/* NOTE: can ack only an internal interrupt cause */
int
AckInternalInt(int n, IEC iec)
{
  switch (iec) {
  case DEV_IEC_CLOCK:
  case DEV_IEC_IPI:
  case DEV_IEC_IPI1:
  case DEV_IEC_IPI2:
    /* just clear int */
    ClearIBit(n, iec);
    return 0;
  default: return -1;
  }
}

/*****************************************************************
 * Migration-Replication support
 *****************************************************************/
void 
MigRepStart(int cpu)
{
   RaiseIBit(cpu, DEV_IEC_MIG_REP);
}

void 
MigRepEnd(int cpu)
{
   ClearIBit(cpu, DEV_IEC_MIG_REP);
}

/****************************************************************************
 *
 * Clock interrupt support
 *
 ****************************************************************************/


/* eventcallback hdr for clock timer */
static EventCallbackHdr timerHdr[SIM_MAXCPUS];
/* clock interrupt counter for stats */
static uint             clockIntrs;
/* maintain last time timer was invoked so that
   we can checkpoint the correct timeleft. */
static SimTime          lastTimeout[SIM_MAXCPUS];


/* timer callback: raise interrupt and enqueue yourself for next tick */
static void
TimerCallback(int cpuNum, EventCallbackHdr *hdr, void *arg)
{
  ASSERT(!USE_MAGIC());
  /* if (CPUVec.drainEvents) { */
  if (0) { 
     /* eventqueue is being cleared, so figure out the timeleft so
      * next CPU model can restart the clock correctly */
     CPUVec.clockStarted[cpuNum] = 0;
     
     SBase[cpuNum].clockTimeLeft = SBase[cpuNum].clockInterval - 
        (CPUVec.CycleCount(cpuNum) - lastTimeout[cpuNum])/CPU_CLOCK;
     if (SBase[cpuNum].clockTimeLeft > SBase[cpuNum].clockInterval)
        SBase[cpuNum].clockTimeLeft = SBase[cpuNum].clockInterval;
     return;
  }
  
  lastTimeout[cpuNum] = CPUVec.CycleCount(cpuNum);
  clockIntrs++;

  RaiseIBit(cpuNum, DEV_IEC_CLOCK);
  CPUVec.IntrBitsChanged(cpuNum);
    
  EventDoCallback(cpuNum, TimerCallback, hdr, NULL,
		  CPUVec.clockInterval[cpuNum] * CPU_CLOCK);
}

/* sets up the callback data and the first callback */
void
InstallTimer(int cpuNum, unsigned int interval, unsigned int timeLeft)
{
  ASSERT(!USE_MAGIC());

  CPUVec.clockInterval[cpuNum] = interval;
  
  if (CPUVec.clockStarted[cpuNum]) EventCallbackRemove(&timerHdr[cpuNum]);
  CPUVec.clockStarted[cpuNum] = 1;

  EventDoCallback(cpuNum, TimerCallback, &timerHdr[cpuNum], NULL, 
		  timeLeft * CPU_CLOCK);

  SBase[cpuNum].clockInterval = CPUVec.clockInterval[cpuNum];
  SBase[cpuNum].clockStarted = CPUVec.clockStarted[cpuNum];
}

/* called when restoring from a checkpoint */
void
InstallTimers(void)
{
  int i;

  for(i = 0; i < TOTAL_CPUS; i++) {
     if (SBase[i].clockStarted) {
        if (USE_MAGIC()) {
           FlashliteInstallTimer(i, SBase[i].clockInterval, SBase[i].clockTimeLeft);
        } else {
           InstallTimer(i, SBase[i].clockInterval, SBase[i].clockTimeLeft);
        }
     }
  }
}

/* called when checkpointing, so that timeLeft field can be updated. */
void
TimerUpdateTimeLeft(void)
{
  int cpuNum;
  for(cpuNum = 0; cpuNum < TOTAL_CPUS; cpuNum++)
    if (SBase[cpuNum].clockStarted) {
      SBase[cpuNum].clockTimeLeft = SBase[cpuNum].clockInterval - 
	     (CPUVec.CycleCount(cpuNum) - lastTimeout[cpuNum])/CPU_CLOCK;
      if (SBase[cpuNum].clockTimeLeft > SBase[cpuNum].clockInterval)
	SBase[cpuNum].clockTimeLeft = SBase[cpuNum].clockInterval;
    }
}

#if 0
/****************************************************************************
 *
 * Device registers and interrupt emulation
 *
 ****************************************************************************/

/*
 * DISK device.
 * The shadow array is indexed by:
 *   - absolute node number (i.e. NOT machine-relative one)
 *   - controller number
 *   - disk unit number
 */
static DevDiskRegisters**** disk_shadow;
#define DISK_SHADOW(_NODE,_CTRL,_UNIT) (*disk_shadow[_NODE][_CTRL][_UNIT])

static void
disk_initialize(void)
{
  disk_shadow = (DevDiskRegisters****)
    ZMALLOC(DISK_NODES*sizeof(DevDiskRegisters***), "disk_shadow");
}

static void
disk_touch(int node, int ctrl, int unit)
{
  char name[32];
  int  nc = NUM_DISK_CONTROLLERS(M_FROM_CPU(node), MCPU_FROM_CPU(node));
  int  uc = DEV_DISK_MAX_UNIT / nc;

  ASSERT(0 <= node && node < DISK_NODES &&
	 0 <= ctrl && ctrl < nc         &&
	 0 <= unit && unit < uc);

  if (!disk_shadow[node]) {
    sprintf(name, "disk_shadow[%d]", node);
    disk_shadow[node] = (DevDiskRegisters***)
      ZMALLOC(nc*sizeof(DevDiskRegisters**), name);
  }
  if (!disk_shadow[node][ctrl]) {
    sprintf(name, "disk_shadow[%d][%d]", node, ctrl);
    disk_shadow[node][ctrl] = (DevDiskRegisters**)
      ZMALLOC(uc*sizeof(DevDiskRegisters*), name);
  }
  if (!disk_shadow[node][ctrl][unit]) {
    sprintf(name, "disk_shadow[%d][%d][%d]", node, ctrl, unit);
    disk_shadow[node][ctrl][unit] = (DevDiskRegisters*)
      ZMALLOC(sizeof(DevDiskRegisters), name);
    sim_disk_touch(node, ctrl, unit);
  }
}


static void
disk_status_update(int node, int ctrl, int unit)
{
  int done, bytes_tr, errno_val;
  DevDiskRegisters* regs = &DISK_SHADOW(node,ctrl,unit);

  sim_disk_status(node, ctrl, unit,
		  &done, &bytes_tr, &errno_val);

  regs->intr_pending     = (DevRegister)done;
  regs->bytesTransferred = (DevRegister)bytes_tr;
  regs->errnoVal         = (DevRegister)errno_val;
  regs->doneIO           = (DevRegister)done;
}

/*
 * Note: when running multiple machines, the following routine
 * is called with an absolute node number (i.e. not a machine-
 * relative one).
 */
static int
disk_handler(int node, int nd, int doff, int type, void* buff)
{
   int          nc    = NUM_DISK_CONTROLLERS(M_FROM_CPU(node),
                                             MCPU_FROM_CPU(node));
   int          uc    = DEV_DISK_MAX_UNIT / nc;
   int          ctrl  = nd / uc; /* controller */
   int          unit  = nd % uc; /* unit attached to controller */
   DevRegister* datap = (DevRegister*)buff;

   ASSERT(0 <= node && node < DISK_NODES &&
          0 <= ctrl && ctrl < nc         &&
          0 <= unit && unit < uc);

#if (DEBUG_MAGIC == 1)
   LogEntry("disk_handler", CPUVec.CurrentCpuNum(),
            "node=%d ctrl=%d unit=%d doff=0x%x t=%d data=0x%08x\n",
            node, ctrl, unit, doff, type, *datap);
#endif

   disk_touch(node, ctrl, unit);
  
  /* we only handle dword accesses and buserror all others */
   ASSERT (BDOOR_SIZE(type) == sizeof(DevRegister));
  
   if (doff == offsetof(DevDiskRegisters, intr_pending)) {
    
      if (BDOOR_IS_LOAD(type)) {
         /* note: bogus mapping (n,nd) -> SimOS disk #. To be improved */
         disk_status_update(node, ctrl, unit);
         *datap = DISK_SHADOW(node,ctrl,unit).intr_pending;
      } else {
         /* note: bogus mapping (n,nd) -> SimOS disk #. To be improved */
         sim_disk_iodone(node, ctrl, unit);
         disk_status_update(node, ctrl, unit);
      }
    
   } else if (doff == offsetof(DevDiskRegisters, errnoVal)) {
    
      if (BDOOR_IS_STORE(type)) goto illegal;
      disk_status_update(node, ctrl, unit);
      *datap = DISK_SHADOW(node,ctrl,unit).errnoVal;

   } else if (doff == offsetof(DevDiskRegisters, bytesTransferred)) {
    
      if (BDOOR_IS_STORE(type)) goto illegal;
      disk_status_update(node, ctrl, unit);
      *datap = DISK_SHADOW(node,ctrl,unit).bytesTransferred;
    
   } else if (doff == offsetof(DevDiskRegisters, interruptNode)) {
    
      /* interruptNode is always the first cpu of the
     * cell in the current implementation.
     * Writes to this register have no effect.
     */
      if (BDOOR_IS_LOAD(type)) *datap = (DevRegister)0;
    
   } else if (doff >= offsetof(DevDiskRegisters, k0Addr[0]) &&
              doff <= offsetof(DevDiskRegisters,
                               k0Addr[DEV_DISK_MAX_DMA_LENGTH-1])) {
    
      int ix = (doff-offsetof(DevDiskRegisters, k0Addr[0])) /
         sizeof(DevRegister);
      if (BDOOR_IS_LOAD(type)) {
         *datap = DISK_SHADOW(node,ctrl,unit).k0Addr[ix];
      } else {
         DISK_SHADOW(node,ctrl,unit).k0Addr[ix] = *datap;
      }
    
   } else if (doff == offsetof(DevDiskRegisters, offset)) {
    
      if (BDOOR_IS_LOAD(type)) {
         *datap = DISK_SHADOW(node,ctrl,unit).offset;
      } else {
         DISK_SHADOW(node,ctrl,unit).offset = *datap;
      }
    
   } else if (doff >= offsetof(DevDiskRegisters, command[0]) &&
              doff <= offsetof(DevDiskRegisters, command[DEV_DISK_CMD_SIZE-1])) {
    
      int ix = (doff-offsetof(DevDiskRegisters, command[0])) /
         sizeof(DevRegister);
      if (BDOOR_IS_LOAD(type)) {
         *datap = DISK_SHADOW(node,ctrl,unit).command[ix];
      } else {
         DISK_SHADOW(node,ctrl,unit).command[ix] = *datap;
      }    
   } else if (doff == offsetof(DevDiskRegisters, startIO)) {
    
      unsigned char cmd[SIM_DISK_CMD_SIZE];
      PA            pages[SIM_DISK_MAX_DMA_LENGTH];
      int           i;
    
      if (BDOOR_IS_LOAD(type)) goto illegal;
    
      /* note: bogus mapping (n,nd) -> SimOS disk #. To be improved */
      ASSERT(DEV_DISK_MAX_DMA_LENGTH <= SIM_DISK_MAX_DMA_LENGTH);
      ASSERT(DEV_DISK_CMD_SIZE <= SIM_DISK_CMD_SIZE);
    
      for (i = 0; i < SIM_DISK_CMD_SIZE; i++)
         cmd[i] = (unsigned char)DISK_SHADOW(node,ctrl,unit).command[i];
      for (i = 0; i < SIM_DISK_MAX_DMA_LENGTH; i++)
         pages[i] = DISK_SHADOW(node,ctrl,unit).k0Addr[i];
    
      sim_disk_startio(node, ctrl, unit,
                       cmd, pages, (int)DISK_SHADOW(node,ctrl,unit).offset);
    
   } else if (doff == offsetof(DevDiskRegisters, doneIO)) {
    
      if (BDOOR_IS_LOAD(type)) goto illegal;
      /* write is (almost) a no-op */
      DISK_SHADOW(node,ctrl,unit).doneIO = (DevRegister)0;
    
   } else {
      /* bad disk offset */
      ASSERT(0);
      return 0;
   }
   return 0;
  
illegal: /* illegal access type */
   ASSERT(0);
   return 1;
}
#endif

static void
disk_interrupt(int node, int ctrl, int unit, int on)
{
  int cpu;

  /* cpu to which interrupt is directed */
  if (inCellMode) {
    /* in cell mode (1 machine), node is absolute CPU number.
     * Must send interrupt to first CPU of that cell.
     */
    cpu = (node / CPUS_PER_CELL(0)) * CPUS_PER_CELL(0); /* CPU 0 in cell */
  } else {
    /* otherwise, node encodes both a machine number and a node.
     * Must send interrupt to first CPU in that machine.
     */
    cpu = FIRST_CPU(M_FROM_CPU(node));
  }

#if (DEBUG_MAGIC == 1)
  LogEntry("disk_interrupt", CPUVec.CurrentCpuNum(),
	   "node=%d ctrl=%d unit=%d cpu=%d on=%d\n",
	   node, ctrl, unit, cpu, on);
#endif

  if (on) RaiseSlot(cpu, DEV_PCI_DISK_SLOT);
  else    ClearSlot(cpu, DEV_PCI_DISK_SLOT);
}


/* CONSOLE device.
 *
 */
static int
console_handler(int cpuNum, int n, int offs, int type, void* buff)
{
  DevRegister* datap = (DevRegister*)buff;
  int        console;

  if (inCellMode) {
    console = n / CPUS_PER_CELL(0); /* XXX one console / cell */
  } else {
    console = FIRST_CONSOLE(M_FROM_CPU(cpuNum)) + n;
  }

#if (DEBUG_MAGIC == 1)
  LogEntry("console_handler", cpuNum, "console=%d offs=0x%x t=%d data=0x%08x\n",
	   console, offs, type, *datap);
#endif

  /* we only handle DevRegister accesses and buserror all others */
  ASSERT (BDOOR_SIZE(type) == sizeof(DevRegister));

  switch (offs) {

  case offsetof(DevConsoleRegisters, intr_status):
     if (BDOOR_IS_LOAD(type)) {
        *datap = HO2BE_4((DevRegister) sim_console_int_status(console));
     } else {
        sim_console_int_set(console, BE2HO_4((int)*datap));
     }
     break;

  case offsetof(DevConsoleRegisters, data):
     if (BDOOR_IS_LOAD(type)) {
        *datap = HO2BE_4((DevRegister) sim_console_in(console));
     } else {
        sim_console_out(console, (char)BE2HO_4(*datap));
     }
     break;

  default: ASSERT(0);
  }
  return 0;
}

static void
console_interrupt(int n, int on)
{
  int cpu;

  if (inCellMode) {
     /* always interrupts first CPU in cell */
     cpu = n * CPUS_PER_CELL(0);
  } else {
     cpu = FIRST_CPU(M_FROM_CONSOLE(n));
  }
  if (on) RaiseSlot(cpu, DEV_PCI_CONSOLE_SLOT);
  else    ClearSlot(cpu, DEV_PCI_CONSOLE_SLOT);
}


#if 0
/* ETHERNET device.
 *
 */
int
ether_handler(int cpuNum, int n, int offs, int type, void* buff)
{
  DevRegister* datap = (DevRegister*)buff;
  int          ctrl;

  if (inCellMode) {
    ctrl = n / CPUS_PER_CELL(0); /* XXX one console / cell */
  } else {
    ctrl = FIRST_ETHER_CONTROLLER(M_FROM_CPU(cpuNum)) + n;
  }

#if (DEBUG_MAGIC == 1)
  LogEntry("ether_handler", cpuNum, "ctrl=%d offs=0x%x t=%d data=0x%08x\n",
	   ctrl, offs, type, *datap);
#endif

  /* we only handle dword accesses and buserror all others */
  ASSERT (BDOOR_SIZE(type) == sizeof(DevRegister));

  /* NOTE: it so "happens" that the SimetherRegisters structure is
   * isomorphic to DevEtherRegisters. This helps us simplify the
   * mapping from the simulated registers to the ether simulator.
   */

  if (BDOOR_IS_LOAD(type)) {
    *datap = (DevRegister)SimetherIO(ctrl, offs, 0, (DevRegister)0);
  } else {
    (void)SimetherIO(ctrl, offs, 1, (DevRegister)*datap);
  }
  return 0;
}
#endif

static void
ether_interrupt(int n, int on)
{
  /* always interrupt first cpu in cell */
  int cpu;
  if (inCellMode) {
     cpu = n * CPUS_PER_CELL(0);
  } else {
     cpu = FIRST_CPU(M_FROM_ETHER_CONTROLLER(n));
  }
  if (on) RaiseSlot(cpu, DEV_PCI_ETHER_SLOT);
  else    ClearSlot(cpu, DEV_PCI_ETHER_SLOT);
}

#if 0
/* A fundamental assumption of simether.c is that the DevEtherRegisters
 * (machine_defs.h) and the SimetherRegisters structures are isomorphic.
 * We'd better check for this.
 */
static void
check_ether_offs(void)
{
  ASSERT(offsetof(DevEtherRegisters, etheraddr[0]) == 
	 offsetof(SimetherRegisters, etheraddr[0]));
  ASSERT(offsetof(DevEtherRegisters, numRcvEntries) == 
	offsetof(SimetherRegisters, numRcvEntries));
  ASSERT(offsetof(DevEtherRegisters, numSndEntries) ==
	 offsetof(SimetherRegisters, numSndEntries));
  ASSERT(offsetof(DevEtherRegisters, numSndChunks) ==
	 offsetof(SimetherRegisters, numSndChunks));
  ASSERT(offsetof(DevEtherRegisters, rcvEntries[0].pAddr) ==
	 offsetof(SimetherRegisters, rcvEntries[0].pAddr));
  ASSERT(offsetof(DevEtherRegisters, rcvEntries[0].maxLen) ==
	 offsetof(SimetherRegisters, rcvEntries[0].maxLen));
  ASSERT(offsetof(DevEtherRegisters, rcvEntries[0].len) ==
	 offsetof(SimetherRegisters, rcvEntries[0].len));
  ASSERT(offsetof(DevEtherRegisters, rcvEntries[0].flag) ==
	 offsetof(SimetherRegisters, rcvEntries[0].flag));
  ASSERT(offsetof(DevEtherRegisters, sndEntries[0].firstChunk) ==
	 offsetof(SimetherRegisters, sndEntries[0].firstChunk));
  ASSERT(offsetof(DevEtherRegisters, sndEntries[0].lastChunk) ==
	 offsetof(SimetherRegisters, sndEntries[0].lastChunk));
  ASSERT(offsetof(DevEtherRegisters, sndEntries[0].flag) ==
	 offsetof(SimetherRegisters, sndEntries[0].flag));
  ASSERT(offsetof(DevEtherRegisters, sndChunks[0].pAddr) ==
	 offsetof(SimetherRegisters, sndChunks[0].pAddr));
  ASSERT(offsetof(DevEtherRegisters, sndChunks[0].len) ==
	 offsetof(SimetherRegisters, sndChunks[0].len));
}
#endif


/* CMOS RT clock device.
 *
 */
static int
clock_handler(int cpuNum, int n, int offs, int type, void* buff)
{
  DevRegister* datap = (DevRegister*)buff;

  ASSERT (BDOOR_SIZE(type) == sizeof(DevRegister));

  if (BDOOR_IS_LOAD(type)) {
     int secsSinceStart = CyclesToNanoSecs(CPUVec.CycleCount(cpuNum))/1000000000;
    *datap = (DevRegister)(machines.InitialTime + secsSinceStart);
  } else {
    ASSERT(0); /* for debugging */
    return 1;  /* clock register not writable */
  }
  return 0;
}



/****************************************************************************
 *
 * MAGIC initialization / registry code
 *
 ****************************************************************************/

#define VA_NODE(va) (((va) >> __MAGIC_NODE_OFFS) & \
		     ((1<<__MAGIC_NODE_BITS)-1))
#define VA_ZONE(va) (((va) >> __MAGIC_ZONE_OFFS) & \
		     ((1<<__MAGIC_ZONE_BITS)-1))
#define VA_REG(va) (((va) >> __MAGIC_REG_OFFS) & \
		    ((1<<__MAGIC_REG_BITS)-1))
#define VA_GRP(va) (((va) >> __MAGIC_PPC_GRP_OFFS) & \
		    ((1<<__MAGIC_PPC_GRP_BITS)-1))
#define VA_OPC(va) (((va) >> __MAGIC_PPC_OPC_OFFS) & \
		    ((1<<__MAGIC_PPC_OPC_BITS)-1))
#define VA_SEQ(va) (((va) >> __MAGIC_PPC_SEQ_OFFS) & \
		    ((1<<__MAGIC_PPC_SEQ_BITS)-1))
#ifdef BBPLAYER
#define VA_OFFS(va) ((va) & ((1<<26)-1))
#else
#define VA_OFFS(va) ((va) & ((1<<__MAGIC_ZONE_OFFS)-1))
#endif

#if 0
static int
FPROM_access(int cpuNum, uint VA, int type, uint* buff)
{
   /* boot prom must be initialized, else this is a bus error */
   /* ASSERT(sim_misc.fprom != NULL); */
   if (sim_misc.fprom[cpuNum] == NULL) {
      return BUSERROR;  
   }

  ASSERT(!USE_MAGIC() || !FPromUseFL);
  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_FPROM_ALIAS);

  ASSERT(VA_OFFS(VA) < FPROM_SIZE);
#define WRITABLE_ROM
#ifdef WRITABLE_ROM
  if (BDOOR_IS_STORE(type)) {
    CPUWarning("Warning: writing to rom address 0x%x\n", (int)VA);
  }
#endif
  switch (type) {
  case BDOOR_LOAD_BYTE:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(byte *)buff = *(byte *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]);
     break;
  case BDOOR_LOAD_HALF:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(unsigned short *)buff = *(unsigned short *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]);
     break;
  case BDOOR_LOAD_WORD:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(uint *)buff = *(uint *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]);
     break;
  case BDOOR_LOAD_DOUBLE:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(uint64*)buff = *(uint64*)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]);
     break;
#ifdef WRITABLE_ROM
  case BDOOR_STORE_BYTE:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(byte *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]) = *(byte *)buff;
     break;
  case BDOOR_STORE_HALF:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(unsigned short *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]) = *(unsigned short *)buff;
     break;
  case BDOOR_STORE_WORD:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(uint *)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]) = *(uint *)buff;
     break;
  case BDOOR_STORE_DOUBLE:
     ASSERT(VA_OFFS(VA) < FPROM_SIZE);
     *(uint64*)(VA_OFFS(VA)+sim_misc.fprom[cpuNum]) = *(uint64*)buff;
     break;
#endif
  default:
     CPUError("FPROM access is not supported by type %d", type);
  }
  return 0;
}
#endif

static int
FRAM_access(int cpuNum, uint VA, int type, uint* buff)
{
  void* addr = (void*)SIM_MEM_ADDR(cpuNum);
  /* boot prom must be initialized */
#if 0
  ASSERT(sim_misc.fprom[cpuNum] != NULL);
  ASSERT(!USE_MAGIC() || !FPromUseFL);
  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_FRAM_ALIAS);
#endif

#ifdef LARGE_SIMULATION
  if (VA_NODE(VA) == 127) {
     /* this is really a fprom access from VA 0xbfc0....  */
     return FPROM_access(cpuNum, VA, type, buff);
  }
#endif

  ASSERT(VA_OFFS(VA) < FRAM_SIZE);

  switch (type) {
  case BDOOR_LOAD_BYTE:
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(byte *)buff = *(byte *)(VA_OFFS(VA)+addr);
     break;
  case BDOOR_LOAD_HALF:
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(unsigned short *)buff = *(unsigned short *)(VA_OFFS(VA)+addr);
     break;
  case BDOOR_LOAD_WORD:
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(uint *)buff = *(uint *)(VA_OFFS(VA)+addr);
     break;
  case BDOOR_LOAD_DOUBLE:
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(uint64*)buff = *(uint64*)(VA_OFFS(VA)+addr);
     break;
  case BDOOR_STORE_BYTE:
     /* also need to check if the fram is writeable during recovery,
      but for now this will do... */
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(byte *)(VA_OFFS(VA)+addr) = *(byte *)buff;
     break;
  case BDOOR_STORE_HALF:
     /* also need to check if the fram is writeable during recovery,
      but for now this will do... */
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(unsigned short *)(VA_OFFS(VA)+addr) = *(unsigned short *)buff;
     break;
  case BDOOR_STORE_WORD:
     /* also need to check if the fram is writeable during recovery,
      but for now this will do... */
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(uint *)(VA_OFFS(VA)+addr) = *(uint *)buff;
     break;
  case BDOOR_STORE_DOUBLE:
     /* also need to check if the fram is writeable during recovery,
      but for now this will do... */
     ASSERT(VA_OFFS(VA) < FRAM_SIZE);
     *(uint64*)(VA_OFFS(VA)+addr) = *(uint64*)buff;
     break;
  default:
     CPUError("FRAM access is not supported by type %d", type);
  }
  return 0;
}

#if 0
static int
BDOOR_disk_access(int cpuNum, uint VA, int type, void* buff)
{
  int node = VA_NODE(VA); /* relative to current machine */
  int offs = VA_OFFS(VA) - __MAGIC_BDOOR_DISKS_OFFS;
  int nd   = offs / sizeof(DevDiskRegisters); /* unit # */
  int doff = offs % sizeof(DevDiskRegisters); /* offset in unit regs */

  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_BDOOR_DEV);

  /* XXX
   * Uncomment the following assert when not using more disk
   * controllers than nodes any longer. Currently, I think this
   * is only used for DISCO. DT.
   * XXX
   */
  /* ASSERT(0 <= node && node < NUM_CPUS(M_FROM_CPU(cpuNum))); */

  /* Note for multiple machines:
   * must translate this access to an absolute node number.
   */
  return disk_handler(node + FIRST_CPU(M_FROM_CPU(cpuNum)),
		      nd, doff, type, buff);
}
#endif

static int
BDOOR_console_access(int cpuNum, uint VA, int type, void* buff)
{
  int n    = VA_NODE(VA);
  int offs = VA_OFFS(VA) - __MAGIC_BDOOR_CNSLE_OFFS;

  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_BDOOR_DEV);
  ASSERT(!inCellMode || (n % CPUS_PER_CELL(0) == 0)); 
  ASSERT(0 <= offs && offs < sizeof(DevConsoleRegisters));

  return console_handler(cpuNum, n, offs, type, buff);
}

#if 0
static int
BDOOR_ether_access(int cpuNum, uint VA, int type, void* buff)
{
  int n    = VA_NODE(VA);
  int offs = VA_OFFS(VA) - __MAGIC_BDOOR_ETHER_OFFS;

  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_BDOOR_DEV);
  ASSERT(!inCellMode || (n % CPUS_PER_CELL(0) == 0)); 
  ASSERT(0 <= offs && offs < sizeof(DevEtherRegisters));

  return ether_handler(cpuNum, n, offs, type, buff);
}
#endif

static int
BDOOR_clock_access(int cpuNum, uint VA, int type, void* buff)
{
  int n    = VA_NODE(VA);
  int offs = VA_OFFS(VA) - __MAGIC_BDOOR_CLOCK_OFFS;

  ASSERT(VA_ZONE(VA) == MAGIC_ZONE_BDOOR_DEV);
  ASSERT(!inCellMode || (n % CPUS_PER_CELL(0) == 0)); 
  ASSERT(0 <= offs && offs < sizeof(DevClockRegisters));

  return clock_handler(cpuNum, n, offs, type, buff);
}

static int
BDOOR_RCP_access(int cpuNum, uint VA, int type, void* buf)
{
  extern int rcp_handler(int node, int nd, int doff, int type, void* buf);
  int n    = 0;
  int offs = VA&0x1fffffff;	/* k1 to phys */
  return rcp_handler(cpuNum, n, offs, type, buf);
}

#if 0
static int
BDOOR_PIF_access(int cpuNum, uint VA, int type, void* buf)
{
  extern int pif_handler(int node, int nd, int doff, int type, void* buf);
  int n    = 0;
  int offs = VA&0x1fffffff;	/* k1 to phys */
  fprintf(stderr, "n64 pif access %08x %08x %08x\r\n", (int)VA, n, offs);
  return pif_handler(cpuNum, n, offs, type, buf);
}
#endif

static int
BDOOR_CD1_access(int cpuNum, uint VA, int type, void* buf)
{
  extern int cd1_handler(int node, int nd, int doff, int type, void* buf);
  int n    = 0;
  int offs = VA&0x1fffffff;	/* k1 to phys */
  fprintf(stderr, "n64 cartridge domain 1 access %08x %08x %08x\r\n", (int)VA, n, offs);
  return cd1_handler(cpuNum, n, offs, type, buf);
  *(int*)buf = 0;
  return 0;
}

static int
BDOOR_RDB_access(int cpuNum, uint VA, int type, void* buf)
{
  extern int rdb_handler(int node, int nd, int doff, int type, void* buf);
  int n    = 0;
  int offs = (int)VA;	/* phys addr */
#if 0
  fprintf(stderr, "n64 rdb access %08x %08x %08x %x %llx\r\n", (int)VA, n, offs, type, (uint64) CPUVec.CurrentPC(cpuNum));
#endif
  return rdb_handler(cpuNum, n, offs, type, buf);
}

#ifdef BBPLAYER
extern int sram_handler(int node, int nd, int doff, int type, void* buf);
extern int virage_handler(int node, int nd, int doff, int type, void* buf);

static int
BDOOR_SRAM_access(int cpuNum, uint VA, int type, void* buf) {
  return sram_handler(cpuNum, 0, (int)VA, type, buf);
}

static int
BDOOR_VIRAGE_access(int cpuNum, uint VA, int type, void* buf) {
  return virage_handler(cpuNum, 0, (int)VA, type, buf);
}
#endif


/* CAVEAT: we currently DON'T model the latency of getting an OSPC
 * cacheline when not running under Flashlite. This is not tragic,
 * but should be fixed at some point.
 */
Result 
sim_magic_MemsysCmd(int cpunum, int cmd, unsigned int paddr,
                    int transId,  unsigned int replacedPaddr, 
                    int writeback, byte *data)
{
  /* Main memory access -- pass on unaffected */
  return memsysVec.MemsysCmd(cpunum, cmd, paddr, transId,
                               replacedPaddr, writeback, data);
}


/*
 * Device polling. Some simulated devices which take asynchronous
 * input from the "real world" need to have a poll function called
 * periodically to check for input.
 */
static EventCallbackHdr pollHdr;	/* poll devices callback */

static void PollDevices(int cpuNum, EventCallbackHdr *hdr, void *arg)
{
  extern void sim_rcp_poll(void);
#if (DEBUG_MAGIC == 1)
  LogEntry("PollDevices", 0, "\n");
#endif

  /* 1. Poll all consoles */
  sim_console_poll();
  /* 2. Poll all ethernet interfaces */
#ifndef linux
  SimetherPoll();
#endif
  sim_rcp_poll();

  /* register callback for next poll round */
  EventDoCallback(0, PollDevices, &pollHdr, NULL, MAGIC_POLL_INTERVAL);
}

void InstallPoller(void)
{
  static int installed = 0;
  if (!installed) {
    installed = 1;
    EventDoCallback(0, PollDevices, &pollHdr, NULL, MAGIC_POLL_INTERVAL);
  }
}


/* ***
 * *** MAGIC & devices initialization.
 * ***
 * *** Initialize all devices, device polling, MAGIC emulation, etc.
 * ***
 */

static void
InitDevices(int restoreFromChkpt)
{

  /*
   * CPUVector
   */
  
  CPUVec.UncachedPIO = SimMagic_DoPIO;

  /* disks */
  {
    int m, n, uc = NUM_UNITS_PER_CONTROLLER(0);
    for (m = 0; m < NUM_MACHINES; m++)
      for (n = 0; n < TOTAL_CPUS; n++) {
	ASSERT(NUM_UNITS_PER_CONTROLLER(m) * NUM_DISK_CONTROLLERS(m,n) <=
	       DEV_DISK_MAX_UNIT);
	ASSERT(uc == NUM_UNITS_PER_CONTROLLER(m));
      }
  }
  sim_disk_init(DISK_NODES,
		NUM_UNITS_PER_CONTROLLER(0),
		disk_interrupt, restoreFromChkpt);

  /* ethernet interfaces */
  SimetherInit(restoreFromChkpt, ether_interrupt);

  /* consoles */
  sim_console_init(TOTAL_CONSOLES, console_interrupt);

  rcp_init();


  /* NOTE: at this point, we'd also like to initialize polling (for those
   * devices that need it). Unfortunately, this depends on the CPUVec
   * being more completely initialized than it is now (before any CPU
   * simulator has started). So we'll let the CPU simulators call
   * InstallPoller().
   */

  /* 4. Checkpointing stuff */
  Simcpt_Register("magic", SimMagic_CheckpointCB, ALL_CPUS);

  if (restoreFromChkpt) Simcpt_Restore("magic");
}

static void
BuildDeviceToMachine(void)
{
   int machNo, count;

   /*
    * Build the arrays that map from device number back to machine number
    */
   
   deviceToMachine.console = (int*)malloc(TOTAL_CONSOLES*sizeof(int));
   deviceToMachine.ether = (int*)malloc(TOTAL_ETHER_CONTROLLERS*sizeof(int));
   deviceToMachine.clock = (int*)malloc(TOTAL_CLOCKS*sizeof(int));
   ASSERT(deviceToMachine.console);
   ASSERT(deviceToMachine.ether);
   ASSERT(deviceToMachine.clock);

   for (machNo = 0; machNo < NUM_MACHINES; machNo++) {
      for (count = FIRST_CONSOLE(machNo);
           count <= LAST_CONSOLE(machNo); count++) {
         deviceToMachine.console[count] = machNo;
      }
      for (count = FIRST_ETHER_CONTROLLER(machNo);
           count <= LAST_ETHER_CONTROLLER(machNo); count++) {
         deviceToMachine.ether[count] = machNo;
      }
      for (count = FIRST_CLOCK(machNo);
           count <= LAST_CLOCK(machNo); count++) {
         deviceToMachine.clock[count] = machNo;
      }
   }
}



#define ZONE_SZ (1 << __MAGIC_ZONE_OFFS)

void
sim_magic_init(int restoreFromChkpt)
{
  int n;
  char name[128];

  if (inCellMode) {
     ASSERT((NUM_CPUS(0) / NUM_CELLS(0)) * NUM_CELLS(0) == NUM_CPUS(0)); 
  }

  CHECK_FOR_COMPILER_BUG;
  CHECK_FOR_COMPILER_BUG2;

  BuildDeviceToMachine();

  /* 1. Initialize service ranges for all nodes */

  /* FRAM alias */
  sprintf(name, "FRAM alias %d", 0);
  RegistryAddRange((VA)__MAGIC_ZONE(0, 0, MAGIC_ZONE_FRAM_ALIAS), 8*ZONE_SZ,
                      REG_FUNC, (void*)FRAM_access, name);
     
#ifdef BBPLAYER
  /* handle the whole Boot RAM/ROM space together */
  RegistryAddRange((VA)_SEXT(0xbfc00000), 65536,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "Boot ROM");
#else
  sprintf(name, "FPROM alias %d", 0);
  RegistryAddRange((VA)FPROM_BASE, 0x7c0,	/* PIF ROM */
                      REG_FUNC, (void*)FPROM_access, name);
  RegistryAddRange((VA)FPROM_BASE+0x7c0, 64,	/* PIF RAM */
                      REG_FUNC, (void*)BDOOR_PIF_access, "PIF RAM");
#endif
  RegistryAddRange((VA)_SEXT(0xbff00000), 64,	/* cartridge domain 1 debug */
                      REG_FUNC, (void*)BDOOR_CD1_access, "Debug Thingy");
  RegistryAddRange((VA)_SEXT(0xb0000000), 64*1024*1024,	/* cartridge domain 1 */
                      REG_FUNC, (void*)BDOOR_CD1_access, "Cartridge Domain 1 0xb window");
  RegistryAddRange((VA)_SEXT(0xa6000000), 32*1024*1024,	/* cartridge domain 1 */
                      REG_FUNC, (void*)BDOOR_CD1_access, "Cartridge Domain 1 0x06 window");
  RegistryAddRange((VA)__MAGIC_ZONE(0, 0, 16*4), 16*ZONE_SZ,
                      REG_FUNC, (void*)BDOOR_RCP_access, "RCP");
  RegistryAddRange((VA)_SEXT(0x80000000), 4096,
                      REG_FUNC, (void*)BDOOR_RDB_access, "RDB");
#ifdef BBPLAYER
  RegistryAddRange((VA)_SEXT(0xbfc20000), 65536,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "Boot RAM");
  RegistryAddRange((VA)_SEXT(0xbfc40000), 32768,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "IRAM");
  RegistryAddRange((VA)_SEXT(0xbfc80000), 64,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "Virage0");
  RegistryAddRange((VA)_SEXT(0xbfc90000), 64,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "Virage1");
  RegistryAddRange((VA)_SEXT(0xbfca0000), 256,
                      REG_FUNC, (void*)BDOOR_SRAM_access, "Virage2");
  RegistryAddRange((VA)_SEXT(0xbfc88000), 32768,
                      REG_FUNC, (void*)BDOOR_VIRAGE_access, "Virage0 Ctl");
  RegistryAddRange((VA)_SEXT(0xbfc98000), 32768,
                      REG_FUNC, (void*)BDOOR_VIRAGE_access, "Virage1 Ctl");
  RegistryAddRange((VA)_SEXT(0xbfca8000), 32768,
                      REG_FUNC, (void*)BDOOR_VIRAGE_access, "Virage2 Ctl");
#endif

  /*
   * Add all the devices to the registry.
   * Add devices are numbered 0 to the MAXVAL-1
   * Here we map the address spaces for the largest number of devices on any
   * one machine.
   * When using cells, they are numbered by cell.
   * Use M_FROM_CONSOLE, M_FROM_ETHER_CONTROLLER,
   * or M_FROM_CLOCK to find machine number.
   */
  
#if 0 /* no disk for now */
  /* XXX caveat DISCO XXX */
  for (n = 0; n < DISK_NODES; n++) {
     sprintf(name, "DevDiskRegisters %d", n);
     RegistryAddRange((VA)(__MAGIC_ZONE(n, 0, MAGIC_ZONE_BDOOR_DEV) +
                           __MAGIC_BDOOR_DISKS_OFFS),
                      sizeof(DevDiskRegisters)*DEV_DISK_MAX_UNIT,
                      REG_FUNC, (void*)BDOOR_disk_access, name);
  }
#endif
  for (n = 0; n < MAX_CONSOLES_PER_MACHINE; n++) {
     int node = n * CPUS_PER_CELL(0);
     sprintf(name, "DevConsoleRegisters %d", node);
     RegistryAddRange((VA)(__MAGIC_ZONE(node, 0, MAGIC_ZONE_BDOOR_DEV) +
                           __MAGIC_BDOOR_CNSLE_OFFS),
                      sizeof(DevConsoleRegisters),
                      REG_FUNC, (void*)BDOOR_console_access, name);
  }
#if 0 /* no ethernet for now */
  check_ether_offs();
  for (n = 0; n < MAX_ETHER_CONTROLLERS_PER_MACHINE; n++) {
     int node = n * CPUS_PER_CELL(0);
     sprintf(name, "DevEtherRegisters %d", node);
     RegistryAddRange((VA)(__MAGIC_ZONE(node, 0, MAGIC_ZONE_BDOOR_DEV) +
                           __MAGIC_BDOOR_ETHER_OFFS),
                      sizeof(DevEtherRegisters),
                      REG_FUNC, (void*)BDOOR_ether_access, name);
  }
#endif
  for (n = 0; n < MAX_CLOCKS_PER_MACHINE; n++) {
     int node = n * CPUS_PER_CELL(0);
     sprintf(name, "DevClockRegisters %d", node);
     RegistryAddRange((VA)(__MAGIC_ZONE(node, 0, MAGIC_ZONE_BDOOR_DEV) +
                           __MAGIC_BDOOR_CLOCK_OFFS),
                      sizeof(DevClockRegisters),
                      REG_FUNC, (void*)BDOOR_clock_access, name);
  }
  
  RegistryDumpEntries();
#if (DEBUG_MAGIC == 1)
  RegistryDumpEntries();
#endif
  
#if 0
  /* init shadow data structures for disk handlers */
  disk_initialize();
#endif
  
  InitDevices(restoreFromChkpt);
  RegistryComplete();
}


/****************************************************************************
 *
 * KSEG1 access type.
 *
 ****************************************************************************/

/*
 * SimMagic_kseg1_accesstype: determine whether a given KSEG1
 *    address should be accessed directly without memory system
 *    activity (SIMMAGIC_DIRECT), passed to the memory system
 *    as an uncached access (SIMMAGIC_UNCACHED) or passed to
 *    the memory system as an accelerated uncached access
 *    (SIMMAGIC_UNCACHED_ACCELERATED).
 *
 * Note that making the distinction between uncached and uncached_accelerated
 * here is purely a workaround, until we improve the OS and the cop0
 * model to construct the access type directly.
 *
 * XXX for now, FRAM and FPROM accesses are handled by sim_magic.c.
 * Need a switch to select beween this (faster) option and the
 * (realistic) one of letting those accesses go to Flite.
 */
SimMagic_accesstype
SimMagic_kseg1_accesstype(uint VA)
{
  switch (VA_ZONE(VA)) {

  case MAGIC_ZONE_FRAM_ALIAS:
#ifndef LARGE_SIMULATION
     /* in large_simulation, fram and fprom zones are the same */
  case MAGIC_ZONE_FPROM_ALIAS:
#endif
    return SIMMAGIC_UNCACHED;

  case MAGIC_ZONE_BDOOR_DEV:
#if (DEBUG_MAGIC == 1)
     CPUPrint("PIO 0x%x\n", VA);
#endif
    return SIMMAGIC_UNCACHED;
  case 64:	/* rcp */
  case 65:
  case 66:
  case 67:
  case 68:
  case 69:
  case 70:
  case 71:
  case 72:
  case 73:
  case 74:
  case 75:
  case 76:
  case 77:
  case 78:
  case 79:
  case 127:	/* cartridge domain 1 */
    return SIMMAGIC_UNCACHED;

  default: break; /* keep compiler happy */
  }
fprintf(stderr, "zone %d VA %x pc %llx\r\n", (int)VA_ZONE(VA), VA, (uint64) CPUVec.CurrentPC(0));
return SIMMAGIC_UNCACHED;
  ASSERT(0);
  return SIMMAGIC_DIRECT;
}


/****************************************************************************
 *
 * Checkpointing support.
 *
 ****************************************************************************/

static int
SimMagic_CheckpointCB(CptDescriptor *cptd)
{
  uint version;
  int  nmagics;

  if (cptVersion.ver == 3) {
     /* XXX NOTE: the following not only _looks_ bogus, it actually _is_.
      * It's this way for compatibility reasons only.
      */
     Simcpt_OptionalUint(cptd, "version", NO_INDEX, NO_INDEX, 0);
     
     version = 3;
     Simcpt_CptUint(cptd, "version", NO_INDEX, NO_INDEX, &version);
     ASSERT(version == 3);
  }
  nmagics = TOTAL_CPUS;
  Simcpt_CptInt(cptd, "numMagics", NO_INDEX, NO_INDEX, &nmagics);
  ASSERT(nmagics == TOTAL_CPUS);

  return 0;
}


static int
MPCheckpointCB(CptDescriptor *cptd)
{
  int cpu, j;
  unsigned char c;

  Simcpt_OptionalInt(cptd, "UseR3kLocks", NO_INDEX, NO_INDEX, 0);

  for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {

    Simcpt_OptionalHex(cptd, "R3k.lockCAShackAddr", cpu, NO_INDEX, 0); 
    Simcpt_OptionalHex(cptd, "SpinLockStartAddr", cpu, NO_INDEX, 0);
    Simcpt_OptionalHex(cptd, "SpinLockEndAddr", cpu, NO_INDEX, 0);

    Simcpt_CptULL(cptd, "iPendingReg", cpu, NO_INDEX, &mm[cpu].iPendingReg);
    if (cptd->mode == CPT_RESTORE) {
      /* compatibility with older checkpoints */
      mm[cpu].iTransReg = mm[cpu].iPendingReg;
    }
    Simcpt_OptionalULL(cptd, "iTransReg", cpu, NO_INDEX, &mm[cpu].iTransReg);
    Simcpt_CptULL(cptd, "iEnableMask", cpu, NO_INDEX, &mm[cpu].iEnableMask);
    for (j = 0; j < 64; j++)
      Simcpt_CptUchar(cptd, "iBitTable", cpu, j, &mm[cpu].iBitTable[j]);

    c = (unsigned char) mm[cpu].IEChigh;
    Simcpt_CptUchar(cptd, "IEChigh", cpu, NO_INDEX, &c);
    mm[cpu].IEChigh = (MagicRegister) c;

    Simcpt_CptInt(cptd, "intrBits", cpu, NO_INDEX, &CPUVec.intrBits[cpu]);

    for (j = 0; j < SIM_MAXSLOTS; j++) {
      int s;
      Simcpt_CptUchar(cptd, "ioSlotMap", cpu, j, &mm[cpu].ioSlotMap[j]);
      s = mm[cpu].ioSlots[j]; /* fudge for compatibility */
      Simcpt_CptInt(cptd, "ioSlots", cpu, j, &s);
      mm[cpu].ioSlots[j] = s;
    }
  }
  return 0;
}


void
sim_magic_cpt(int restoreFromChkpt)
{
  Simcpt_Register("mp", MPCheckpointCB, ALL_CPUS);
  if(restoreFromChkpt) Simcpt_Restore("mp");
}

/* NOTE:  for flashlite, cpuNum is the destination node,
   not the node originating the PIO */
Result
SimMagic_DoPIO(int cpuNum, PA addr, int isRead, int size, void *data)
{
   void *func;
   uint type, flag;
   VA vAddr    = (VA)(Reg32_s)addr; /* Sign extend if needed */
   int inRange = RegistryIsInRange(vAddr, &func, &flag);
   
   if (!inRange) {
      CPUError("PIO out of range pc=0x%llx vAddr=0x%llx \n",
               (uint64) CPUVec.CurrentPC(cpuNum), (uint64)vAddr);
   }
   
   ASSERT(flag & REG_FUNC);
   
   switch (size) {
   case sizeof(char):
      type = isRead ? BDOOR_LOAD_BYTE : BDOOR_STORE_BYTE;
      break;

   case sizeof(short):
      type = isRead ? BDOOR_LOAD_HALF : BDOOR_STORE_HALF;
      break;

   case sizeof(int):
      type = isRead ? BDOOR_LOAD_WORD : BDOOR_STORE_WORD;
      break;

   case sizeof(long long):
      type = isRead ? BDOOR_LOAD_DOUBLE : BDOOR_STORE_DOUBLE;
      break;

   default:
      CPUError("Bad PIO access size %x\n", size);
      type = 0;
   }
   return (Result)((MagicFunction)func)(cpuNum, vAddr, type, data);
}

int
SimMagic_IsIncoherent(uint pAddr)
{
   int pgNum = pAddr / SIM_PAGE_SIZE;
   int byteIndex = pgNum / sizeof(char);
   int bitIndex = pgNum % sizeof(char);

   if (inCellMode) {
      ASSERT(IS_VALID_PA(0, pAddr));
      return (sim_misc.incoherentPages[byteIndex] >> bitIndex) & 1;
   } else
      return 0;
}

void
SimMagic_MakeIncoherent(uint pAddr)
{
   int pgNum = pAddr / SIM_PAGE_SIZE;
   int byteIndex = pgNum / sizeof(char);
   int bitIndex = pgNum % sizeof(char);

   if (inCellMode) {
      ASSERT(IS_VALID_PA(0, pAddr));
      sim_misc.incoherentPages[byteIndex] |= 1 << bitIndex;
   }
}

unsigned char
SimMagic_GetIbitTableEntry(int cpunum, int entry)
{
  return mm[cpunum].iBitTable[entry];
}


uint64
SimMagic_GetIECPending(int cpunum)
{
  return (uint64) mm[cpunum].iPendingReg;
}

uint64
SimMagic_GetIECTrans(int cpunum)
{
  return (uint64) mm[cpunum].iTransReg;
}

uint64
SimMagic_GetIECEnable(int cpunum)
{
  return (uint64) mm[cpunum].iEnableMask;
}

int
sim_magic_OSPC_access(int cpuNum, uint VA, byte *data)
{                                                                               
    ASSERT(0);
    return 0;
}

void
sim_magic_OSPC_stalled(int cpuNum, VA va, int stalled)
{
}

void
sim_sips_deliver(int n, int chan_sender)
{
    ASSERT(0);
}

MA
CacheableDeviceAddress(int machNo, PA pAddr) {
    extern MA sram_addr(int machNo, uint pAddr);
    return sram_addr(machNo, (uint)pAddr);
}