/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/*****************************************************************
 * startup.c
 * 
 * This is the entry point into simos. 
 *
 * $Author: blythe $
 * $Date: 2003/02/21 06:12:23 $
 *****************************************************************/

#include "sim.h"
#define _BSD_SIGNALS 
#include <sys/signal.h>
#ifndef i386
#include <sys/sysinfo.h>
#endif
#include <sys/times.h>
#include <sys/types.h>
#include <sys/errno.h>
#include <sys/termios.h>
#include <sys/time.h>
#include <sys/file.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <netinet/tcp.h>
#include <sys/mman.h>
#include <unistd.h>
#include <fcntl.h>
#include <stdio.h>
#include <setjmp.h>
#include <string.h>
#include <memory.h>
#include <ctype.h>
#include <math.h>
#include <stdlib.h>
#ifdef sgi
#include <sys/sysmp.h>
#endif
#include <sys/wait.h>
#include <netdb.h>
#include "syslimits.h"
#include "cpu_state.h"
#include "startup.h"
#include "checkpoint.h"
#include "machine_params.h"
#include "simmisc.h"
#include "sim_error.h"
#include "registry.h"
#include "simstats.h"
#include "annotations.h"
#include "cpu_interface.h"
#include "simmagic.h"
#include "hd.h"
#include "ethernet.h"
#include "console.h"
#include "eventcallback.h"
#include "dma.h"
#include "../../devices/disk/simos_interface.h"
#include "simutil.h"
#include "hw_events.h"
#include "simtypes.h"
#include "remote_access.h"
#include "gdb_interface.h"
#include "tcl_init.h"
#include "mips_arch.h"
#include "params.h"
#ifdef HWBCOPY
#include "hw_bcopy.h"
#endif

#define SIMOS_VERSION "3.0"


/********************
 * GLOBAL VARIABLES *
 ********************/
/* Leave room for Embra's pseudo-CPU */
CPUState* SBase;
CPUType   simosCPUType = NO_CPU;      /* Global notion of the current simulator */
int       restoringCpt = 0;
int       hostNumProcs = 1;
int hostCPUIdleStats[SIM_MAXHOSTCPUS]; /* %idle for each processor */
int       inCellMode = 0;              /* True if using cells (implies 1 machine) */
char *checkpointName;
SimTime startingCycle[SIM_MAXCPUS];

/**********************
 * EXTERNAL FUNCTIONS *
 **********************/
extern void TCLInit(char *initFile);

/**********************
 * EXTERNAL VARIABLES *
 **********************/
extern char **environ;
extern CptVersion cptVersion;

/********************
 * STATIC VARIABLES *
 ********************/
static int mfd;



/********************
 * STATIC FUNCTIONS *
 ********************/
static void Sigusr(int);

/* Physical memory file checkpoint */
static CptCallback MemoryCheckpointCB;
/* Execution state checkpoint */
static CptCallback ExecStateCheckpointCB;
/* Prom state checkpoint */
static CptCallback PromCheckpointCB;
/* Tcl state checkpoint */
static CptCallback TclCheckpointCB;


/* option processing */

struct {
   int simCheckpointRestore;    /* -r selected */
   char* checkpoint_master;     /* argument to -r */
   CPUType startcpu;            /* -m, -c, -p selected */
   char *fault_file;            /* -f selected */
   char* cpualloc_hostport;     /* argument to -a, nil if -a not selected */
   char* skiplist;              /* argument to -s, nil if -s not selected */
   char* param_file;            /* File with parameter values */
   char* log_file;              /* -l option: log file name */
   char* debug_flags;
   int   debug_intr;            /* debug interrupts? */
} optvals;

/*****************************************************************
 *
 *****************************************************************/
static void
ParseOpts(int argc, char** argv)
{
   int c;
   extern char* optarg;
   extern int optind;
   
   bzero((char*)&optvals, sizeof(optvals));
   optvals.startcpu   = NO_CPU;
   optvals.param_file = "init.simos";
   optvals.log_file   = "cpu.log";
   optvals.debug_flags = "";

   if (getenv("SIMOS_INIT")) optvals.param_file = getenv("SIMOS_INIT");
   while ((c = getopt(argc, argv, "z:r:imcpf:a:s:o:bl:d:")) != EOF) {
       switch (c) {
       case 'r':
	   optvals.simCheckpointRestore = 1;
	   optvals.checkpoint_master = optarg;
           checkpointName = optarg;
	   break;
       case 'm':
	   optvals.startcpu = MIPSY;
	   break;
       case 'z': 
	   optvals.param_file = optarg;
	   break;
       case 'c':
	   optvals.startcpu = EMBRA_CACHE;
	   break;
       case 'd':
           if (!argv[optind - 1]) {
              fprintf(stderr, "SimOS: Turning all debugging flags on\n");
              optvals.debug_flags = "+";
           } else {
              optvals.debug_flags = optarg;
           }
	   break;
       case 'p':
	   optvals.startcpu = EMBRA_PAGE;
	   break;
       case 'a':
	   optvals.cpualloc_hostport = optarg;
	   break;
       case 's':
	   optvals.skiplist = optarg;
	   break;
       case 'f':
	   optvals.fault_file = optarg;
	   break;
       case 'o':
           if (!argv[optind - 1]) {
	     fprintf(stderr, "\nmissing value for option: %s\n", optarg);
	     exit(1);
	   } else if ((optind < argc) && (argv[optind][0] != '-')) {
              TCLDefineOption(optarg, argv[optind]);
              optind++;
           } else {
              TCLDefineOption(optarg, "1");
           }
           break;
       case 'l':
	   optvals.log_file = optarg;
	   break;
       case 'i':
	   optvals.debug_intr = 1;
	   break;
       case '?':
	   fprintf(stderr,
		   "\nusage: simos [-r checkpoint_masterlog] [-m (mipsy)]\n"
		   "    [-c (embra_cache)] [-d <debugflags>] [-p (embra_page)]\n"
		   "    [-z param_file_name] [-f fault_file_name]\n"
		   "    [-o tclopt [val]]  [-l log_file_name]\n");
           exit(1);
       }
   }
}

/*****************************************************************
 * MAIN ENTRY POINT INTO SIMOS
 *****************************************************************/
int
main(int argc, char *argv[], char **env)
{
  char *addr;
  int i, machNo;
    
  /* Clear the machine structure */
  bzero (&machines, sizeof(MachinesStruct));
   
  ParseOpts(argc, argv);

  /* Enable debug flags */
  DebugInit(optvals.debug_flags);

  /* init log file before printing anything */
  SimErrorInit(optvals.log_file);
   
  Sim_Warning("===== SimOS Version %s =====\n", SIMOS_VERSION );

  restoringCpt = optvals.simCheckpointRestore;

  /* Starting cycle should be 0 when starting. */
  if (!restoringCpt) {
     for (i = 0; i < SIM_MAXCPUS; i++) {
        startingCycle[i] = 0;
     }
  }
  
  Simcpt_Init();

  Simcpt_Register("prom", PromCheckpointCB, ALL_CPUS);
  if (restoringCpt) {
     Simcpt_Checkpoint(CPT_RESTORE, optvals.checkpoint_master);
     Simcpt_Restore("prom");
     if (cptVersion.ver == 3) {
        /* XXX
	 * Note (DT): this should go!
	 */
        int m, n;
        /* Read the number of cells and ethernet ctrls (if cpt ver is 3) */
        /* If ver >= 4, then they will already have been read in the prom */
        Simcpt_Preread_Numcells();
        Simcpt_Preread_Numether();
        /* This hack is not required in version 4 cpts, since the num of disk
            controllers and clocks are saved */
        if (NUM_CELLS(0) > 1) {
	  NUM_CLOCKS(0) = NUM_CELLS(0);
	  for (n = 0; n < SIM_MAXCPUS; n++) NUM_DISK_CONTROLLERS(0,n) = 1;
        } else {
	  NUM_CLOCKS(0) = MOOSE_MAXVMS; /* XXX brain damage, REMOVE */
	  for (m = 0 ; m < MAX_MACHINES; m++)
	    for (n = 0; n < SIM_MAXCPUS; n++)
	      NUM_DISK_CONTROLLERS(m,n) = 1;
	}
     }
     
     /* let param manager know which of the parameters have been initialized
      * so it doesn't error the user for forgetting to init them
      */
     ParamGrabbedAtStartup("PARAM(MACHINE.Count)");
     ParamGrabbedAtStartup("PARAM(CPU.Count)");
     ParamGrabbedAtStartup("PARAM(HIVE.NumCells)");
     ParamGrabbedAtStartup("PARAM(MEMSYS.MemSize)");
     ParamGrabbedAtStartup("PARAM(CONSOLE.Count)");
     ParamGrabbedAtStartup("PARAM(ETHERNET.Count)");
     ParamGrabbedAtStartup("PARAM(CLOCK.Count)");
     ParamGrabbedAtStartup("PARAM(DISK.NumControllers)");
  }

  InitCPUModel(optvals.startcpu);

  TCLInit(optvals.param_file);

  Simcpt_Register("tcl", TclCheckpointCB, ALL_CPUS);
  if (restoringCpt) {
    /* restore saved Tcl state, if any */
    Simcpt_Restore("tcl");
  }

  if (simosCPUType == NO_CPU) {
     CPUError("No cpu model specified\n");
  }
  
  CPUPrint("Invocation: ");
  for (i=0; i<argc; i++) CPUPrint("%s ", argv[i]);
  CPUPrint("\n");
  
  RegistryInit();
  
  /* Initialize the base memory address for each machine
   */
  SIM_MEM_ADDR(0) = BASESIMMEMADDR;
  for (machNo = 1; machNo < NUM_MACHINES; machNo++) {
      SIM_MEM_ADDR(machNo) =
          SIM_MEM_ADDR(machNo-1) + MEM_SIZE(machNo-1);
  }
      
  Simcpt_Register("memory", MemoryCheckpointCB, ALL_CPUS);
  Simcpt_UseCompression("memory", GZIP, BIN_FILE_ONLY);

  /* Remap Vector. Not exported to kernel, but in shared memory */
  /* XXX is this still needed? Don;t think so! XXX */
  remapVec = ZMALLOC(sizeof(RemapVector),"RemapVector");

  /* Initialize some values in sim_misc */
  SimMiscInit(optvals.debug_intr);

  /* Initialize MAGIC and devices. */
  sim_magic_init(restoringCpt);

#ifdef HWBCOPY
  /* Initialize hwbcopy */
  Simhwbcopy_init();
#endif
  
  /* 
   * Various  initializations. These all generally need to be done 
   * when the parameters (known when the checkpoint state is
   * restored) are known.  
   */
  
  EventCallbackInit(TOTAL_CPUS);
  DMAInit();
  
  /*
   * Configure disk model. By default we use an accurate model of a SCSI disk.
   * To allow some flexiblity we have the ability to scale the speed of the 
   * disk (simConfigDiskScaling is a number in precent used for scaling, 100%
   * is "real" disk speed. A scaling of 0 or less means model a fixed latency
   * disk using simConfigAsyncDiskDelay as the fixed delay in milliseconds. 
   */
  if (!strcmp(DISK_MODEL(0), "HP")) {
     /* Initialize the DISK model we are compiled for */
     DiskModelInit(SIM_MAX_DISKS, ((double)HP_DISK_SCALING(0))/100.0);
  } else {
     if (strcmp(DISK_MODEL(0), "Fixed")) {
        CPUWarning("Bad disk model: %s\n", DISK_MODEL(0));
        ASSERT(0);
     }
  }

  /* Create the physical memory for the machine. 
   * Initialize the value of memory to zero. 
   * If we are restoring from a checkpoint we do this anyway
   * to make the  restore symmetric with the save. 
   */
  if (restoringCpt ) {
     if (Simcpt_CanMmapMemoryCheckpoint() ) {
        mfd = Simcpt_GetMemoryCptFile();
        if( mfd < 0 ) {
           perror("Open MemFile failed");
           exit(1);
        } 
     } else {
        /* Restore into a local file. */
        mfd = MakeFile(MemFileDir, NULL, 0,1);
        Simcpt_Restore("memory");
     }
     if (mfd < 0) {
        Sim_Error("startup: Can't create memory file\n");
     }  
  } else {
     /* This maps K0 out of /dev/zero which makes */
     /* simos startup and termination much faster */
#ifdef __alpha
     mfd = -1;
#else
     mfd = open("/dev/zero", O_RDWR, 0);
     if (mfd < 0) {
        Sim_Error("startup: Can't create memory file\n");
     }
#endif  
  } 
  
  /*
   * Perform the mmap for each machine (out of the same memory file)
   */
  for (machNo = 0; machNo < NUM_MACHINES; machNo++) {
      SIM_DEBUG(('g', "size = %d\n", MEM_SIZE(machNo)));

#ifdef sgi
      addr = (char *) mmap(SIM_MEM_ADDR(machNo), 
                           MEM_SIZE(machNo) & ~(SIM_PAGE_SIZE-1),
                           PROT_READ|PROT_WRITE|PROT_EXEC, 
                           MAP_PRIVATE|MAP_AUTORESRV,
                           mfd, SIM_MEM_ADDR(machNo)-SIM_MEM_ADDR(0));
      if (addr != SIM_MEM_ADDR(machNo)) {
          perror("mmap of KSEG0");
          exit(1);
      }
#endif
#ifdef sun
      SIM_DEBUG(('g', "map to %#x\n", SIM_MEM_ADDR(machNo)));

      addr = (char *) mmap(SIM_MEM_ADDR(machNo),
                           MEM_SIZE(machNo) & ~(SIM_PAGE_SIZE-1),
                           PROT_READ|PROT_WRITE|PROT_EXEC, 
                           MAP_FIXED|MAP_PRIVATE,
                           mfd, SIM_MEM_ADDR(machNo)-SIM_MEM_ADDR(0));
      if (addr != SIM_MEM_ADDR(machNo)) {
          perror("mmap of KSEG0");
          exit(1);
      }
#endif
#ifdef __alpha
      addr = (char *) mmap(SIM_MEM_ADDR(machNo),
                           MEM_SIZE(machNo),
                           PROT_READ|PROT_WRITE, 
                           MAP_FIXED|MAP_PRIVATE|
                             (mfd>0?MAP_FILE:MAP_ANONYMOUS),
                           mfd, SIM_MEM_ADDR(machNo)-SIM_MEM_ADDR(0));
      CPUWarning("physicalMemory set at 0x%p memSize=%d  \n",
                 addr,MEM_SIZE(machNo));
      if (addr == (void*)-1) { 
          perror("mmap of physical memrory: ");
          exit(1);
      }
#endif

#ifdef linux
      addr = (char *) mmap(SIM_MEM_ADDR(machNo),
                           MEM_SIZE(machNo),
                           PROT_READ|PROT_WRITE,
                           MAP_PRIVATE|MAP_FIXED,
                           mfd, SIM_MEM_ADDR(machNo)-SIM_MEM_ADDR(0));
      if (addr != SIM_MEM_ADDR(machNo)) {
          perror("mmap of KSEG0");
          exit(1);
      }
#endif
  }

  /*
   * ZeroMem initialization. 
   * InitZeroMem simply declares the address range from
   * which memory can be allocated and zeroed, potentially
   * using an mmap of /dev/null.
   */
#ifdef __alpha
  InitZeroMem(SIM_MEM_ADDR(NUM_MACHINES-1) + MEM_SIZE(NUM_MACHINES-1), 
              (char *) 0x300000000,0);
#else
  InitZeroMem(SIM_MEM_ADDR(NUM_MACHINES-1) + MEM_SIZE(NUM_MACHINES-1), 
              (char*)UINT_TO_PTRSIZE(0x70000000), 1 /* yes, redzone the next page */);
#endif
  
  /* XXX support for restoring (part of) MAGIC state from
   * checkpoint. Placed here for compatibility with older
   * SimOS version.
   */
  sim_magic_cpt(restoringCpt);

  /*
   * Initalize memory and interrupt handling.
   */
  
  SBase = (CPUState *) malloc(sizeof(CPUState)*(TOTAL_CPUS+1));
  bzero((char*)SBase,sizeof(CPUState)*(TOTAL_CPUS+1));
  for (i = 0; i < TOTAL_CPUS; i++) {
    int t;

    SBase[i].memoryPtr   = SIM_MEM_ADDR(M_FROM_CPU(i));
    SBase[i].memSize     = MEM_SIZE(M_FROM_CPU(i));
    SBase[i].intrBitsPtr = &CPUVec.intrBits[i];
    SBase[i].myNum       = i;

    for (t = 0; t < MAX_NTLBENTRIES; t++) {
       /* Invalid entry - never matches */
       SBase[i].tlbEntry[t].Hi = (K0BASE & TLBHI_FILLMASK); 
       SBase[i].tlbEntry[t].Lo0 = SBase[i].tlbEntry[t].Lo1 = 0;
    }

    if (strcmp(machines.TlbOrg, "R4000") == 0) {
       SBase[i].CP0[C0_CONFIG] = (3 << CNFIG_IC_SHIFT) | (3 << CNFIG_DC_SHIFT);
       SBase[i].CP0[C0_PRID] = (4 << C0_IMPSHIFT) | (4 << C0_MAJREVSHIFT);
       SBase[i].numTlbEntries = NTLBENTRIES_R4000;
    } else  if (strcmp(machines.TlbOrg, "R10000") == 0) { 
       SBase[i].CP0[C0_CONFIG] = (3 << CNFIG_IC_SHIFT) | (3 << CNFIG_DC_SHIFT);
       SBase[i].CP0[C0_PRID] = (9 << C0_IMPSHIFT) | (2 << C0_MAJREVSHIFT);
       SBase[i].numTlbEntries = NTLBENTRIES_R10000;
    } else {
       Sim_Warning("Unknown TLB.Org value of %s. Using R4000\n", machines.TlbOrg);
       SBase[i].numTlbEntries = NTLBENTRIES_R4000;
    }

    SBase[i].is32bitMode = 1;   /* Put us into 32bit mode */
    SBase[i].notFRbit = 1;      /* With the FR bit not set */

  }
  /*
   * Startup the simulation of the MMU and exception handlers.
   */ 
  Simcpt_Register("execstate", ExecStateCheckpointCB, ALL_CPUS);

  if (restoringCpt) Simcpt_Restore("execstate");
  
  Simdebug_init();
  if (signal(SIGUSR1, Sigusr) == SIG_ERR) perror("signal(SIGUSR1");

  RegistryDumpEntries();

  if (restoringCpt) SimulatorEnter(simosCPUType, 1, 0); /* enter simulator */
  else              SimPromEnter();                     /* enter "bootprom" */

  exit(0);
  return 0;           /* Shut up the compiler */
}



/*
 * Called on a SIGUSR1 signal. Used to enter tcl, etc. 
 */
static void 
Sigusr(int sig)
{
   if (signal(SIGUSR1, Sigusr) == SIG_ERR) perror("signal(SIGUSR1)");

   if (CPUVec.Handle_Debug_Signal) {
      CPUVec.Handle_Debug_Signal(0, (sig == SIGUSR1));
   }
   return;
}


/***************************************************************************
 *
 * Checkpointing routines.
 *
 ***************************************************************************/

static int
MemoryCheckpointCB(CptDescriptor *cptd)
{
   int machNo;

   if (cptVersion.ver == 4 && cptVersion.sub == 0) {
      for (machNo = 0; machNo < NUM_MACHINES; machNo++) {
         Simcpt_CptBlock(cptd, "Memory", machNo, NO_INDEX, 
                         (caddr_t) SIM_MEM_ADDR(machNo),
                         MEM_SIZE(machNo), mfd );
      }
   } else if (cptVersion.ver == 3) {
      Simcpt_CptBlock(cptd, "Memory", NO_INDEX, NO_INDEX, 
                      (caddr_t) SIM_MEM_ADDR(0),
                      MEM_SIZE(0), mfd );
   } else {
      ASSERT(0);
   }
   return 0;
}

#if defined(SIM_MIPS32)
#define Simcpt_CptMipsReg(_cptd, _tag, _cpu, _index, _regPtr)  \
                  Simcpt_CptHex(_cptd, _tag, _cpu, _index, _regPtr) 
#else
#define Simcpt_CptMipsReg(_cptd, _tag, _cpu, _index, _regPtr)  \
                  Simcpt_CptULL(_cptd, _tag, _cpu, _index, _regPtr) 
#endif

static int
ExecStateCheckpointCB(CptDescriptor *cptd)
{
  int cpu, reg, tlb;

  /* For checkpoint ver. 3 compatibility */
  int memSize = MEM_SIZE(0);
  int cpncpu = NUM_CPUS(0);
  SimTime oldStartCycle[SIM_MAXCPUS];

  if (cptd->mode == CPT_SAVE) {
     TimerUpdateTimeLeft();
  }

  if (cptVersion.ver == 3) {
     Simcpt_CptInt(cptd, "MemSize", NO_INDEX, NO_INDEX, &memSize);
     ASSERT(memSize == MEM_SIZE(0));
     Simcpt_CptInt(cptd, "NumCPUs", NO_INDEX, NO_INDEX, &cpncpu);
     ASSERT(cpncpu == NUM_CPUS(0));
  }
  
  for( cpu = 0; cpu < TOTAL_CPUS; cpu++ ) {
    for( reg = 0; reg < 32; reg++ ) {
       Simcpt_CptMipsReg(cptd, "R", cpu, reg, &(SBase[cpu].R[reg]));
    }
    Simcpt_CptMipsReg(cptd, "PC", cpu, NO_INDEX,  &(SBase[cpu].PC));
    Simcpt_CptMipsReg(cptd, "HI", cpu, NO_INDEX,  &(SBase[cpu].HI));
    Simcpt_CptMipsReg(cptd, "LO", cpu, NO_INDEX,  & (SBase[cpu].LO));

    if(IS_KSEG1(SBase[cpu].PC)) {
      /* give a warning only. The user can try to take another one. */
      CPUWarning(" CPU %i is in the backdoor at 0x%08x in the checkpoint -- bad checkpoint!\n", cpu);
    }
    for( reg = 0; reg < 32; reg++ ) {
       Simcpt_CptMipsReg(cptd, "FPR", cpu, reg, &(SBase[cpu].FPR[reg])); 
    }
    Simcpt_CptHex(cptd, "FCR0", cpu, NO_INDEX, &(SBase[cpu].FCR[0]));
    Simcpt_CptHex(cptd, "FCR31", cpu, NO_INDEX, &(SBase[cpu].FCR[31]));

    for( reg = 0; reg < 32; reg++ ) {
       Simcpt_CptMipsReg(cptd, "CP0R", cpu, reg, &(SBase[cpu].CP0[reg]));
    }
    Simcpt_OptionalInt(cptd, "NTLBENTRIES", cpu, NO_INDEX, NTLBENTRIES_R4000);
                                              /* default to 48 (R4000) */
    Simcpt_CptInt(cptd, "NTLBENTRIES", cpu, NO_INDEX, &(SBase[cpu].numTlbEntries));
    for( tlb = 0; tlb < SBase[cpu].numTlbEntries; tlb++ ) {
       Simcpt_OptionalHex(cptd, "TLBPGMSK", cpu, tlb, 0); /* default to 4K size */
       Simcpt_CptHex(cptd, "TLBPGMSK", cpu, tlb, &(SBase[cpu].tlbEntry[tlb].PgMsk));
       Simcpt_CptMipsReg(cptd, "TLBHI", cpu, tlb, &(SBase[cpu].tlbEntry[tlb].Hi));
       Simcpt_CptMipsReg(cptd, "TLBLO0", cpu, tlb, &(SBase[cpu].tlbEntry[tlb].Lo0));
       Simcpt_CptMipsReg(cptd, "TLBLO1", cpu, tlb, &(SBase[cpu].tlbEntry[tlb].Lo1));
    }
    /*
     * External interrupt bits (CHECK THIS???)
     */
    if (SBase[cpu].intrBitsPtr == NULL) {
      SBase[cpu].intrBitsPtr = (int *) malloc(sizeof(int));
      *SBase[cpu].intrBitsPtr = 0;
    }
    Simcpt_CptInt(cptd, "ExtIntrBit", cpu, NO_INDEX, &(*(SBase[cpu].intrBitsPtr)));

    Simcpt_CptUint(cptd, "ClockStarted", cpu, NO_INDEX, &(SBase[cpu].clockStarted));
    Simcpt_CptUint(cptd, "ClockInterval", cpu, NO_INDEX, &(SBase[cpu].clockInterval));
    Simcpt_CptUint(cptd, "ClockTimeLeft", cpu, NO_INDEX, &(SBase[cpu].clockTimeLeft));

    for( reg = 0; reg < 4; reg++ ) {
      Simcpt_CptHex(cptd, "CP0SaveArea", cpu, reg, &(SBase[cpu].cp0savearea[reg]));
    }
    Simcpt_CptHex(cptd, "RemapMask", cpu, NO_INDEX, (uint *) &(remapVec->RemapMask[cpu]));
    Simcpt_CptUchar(cptd, "RemapEnable", cpu, NO_INDEX, &(remapVec->RemapEnable[cpu]));
    Simcpt_CptHex(cptd, "RemapNodeAddr", cpu, NO_INDEX, (uint *) &(remapVec->NodeAddr[cpu]));

    if (cptd->mode == CPT_SAVE) {
       oldStartCycle[cpu] = startingCycle[cpu];
       
       startingCycle[cpu] += CPUVec.CycleCount(cpu);
       CPUWarning("CPT - old time %lld new time %lld\n", 
                  oldStartCycle[cpu], startingCycle[cpu]);
    }
    Simcpt_OptionalULL(cptd, "StartingCycle", cpu, NO_INDEX, 0);
    Simcpt_CptULL(cptd, "StartingCycle", cpu, NO_INDEX, &startingCycle[cpu]);

    if (cptd->mode == CPT_SAVE) {
       if (oldStartCycle[cpu] > 0) {
          startingCycle[cpu] = oldStartCycle[cpu];
       } else {
          startingCycle[cpu] = 0;
       }
    }
  }
  return 0;
}


static int
PromCheckpointCB(CptDescriptor *cptd)
{
   int machNo;

   /*
    * Establish or save the checkpoint version
    */
   
   if (cptd->mode == CPT_SAVE) {
     /* Set the current version to the desired save version */
      cptVersion.ver = cptVersion.saveVer;
      cptVersion.sub = cptVersion.saveSub;
   } 
   Simcpt_CptInt(cptd, "Version", NO_INDEX, NO_INDEX,
                 &(cptVersion.ver));
   if (cptVersion.ver >= 4) {
      Simcpt_CptParamInt(cptd, "SubVersion", NO_INDEX, NO_INDEX,
                         &(cptVersion.sub));
   } else {
      cptVersion.sub = 0;
   }
      
   if (cptd->mode == CPT_SAVE) {
      CPUPrint("CPT: Saving (Format is version %d, sub-version %d)\n",
               cptVersion.ver, cptVersion.sub);
   } else {
      CPUPrint("CPT: Restoring (Format is version %d, sub-version %d)\n",
               cptVersion.ver, cptVersion.sub);
   }
      
   /*
    * Do the checkpointing
    */
   
   if (cptVersion.ver == 4 && cptVersion.sub == 0) {

      Simcpt_CptParamInt(cptd, "NumMachines", NO_INDEX, NO_INDEX,
                         &(NUM_MACHINES));
      
      for (machNo = 0; machNo < NUM_MACHINES; machNo++) {
         Simcpt_CptParamInt(cptd, "NumCPUs", machNo, NO_INDEX,
                            &(NUM_CPUS(machNo)));
         Simcpt_CptParamInt(cptd, "NumCells", machNo, NO_INDEX,
                            &(NUM_CELLS(machNo)));
         Simcpt_CptParamInt(cptd, "MemSize", machNo, NO_INDEX,
                            &(MEM_SIZE(machNo)));
         Simcpt_CptParamInt(cptd, "NumConsoles", machNo, NO_INDEX,
                            &(NUM_CONSOLES(machNo)));
         Simcpt_CptParamInt(cptd, "NumEtherControllers", machNo, NO_INDEX,
                            &(NUM_ETHER_CONTROLLERS(machNo)));
	 {
	   /* NOTE on compatibility:
	    * Former checkpointing code save a total number of disk
	    * controllers per machine. To preserve compatibility with
	    * older checkpoints, we now save the following:
	    *    NumDiskControllers[m] : 0
	    *    NumDiskControllers[m,n] : <ctrls>
	    *    NumUnitsPerController[m] : <upc>
	    * (note the first line should be eventually eliminated).
	    */
	   int nc = 0;
	   Simcpt_CptParamInt(cptd, "NumDiskControllers", machNo, NO_INDEX,
			      &nc);
	   if (nc != 0) {
	     /* compatibility: restoring from old checkpoint */
	     /* note old checkpoints can have more disk-carrying nodes
	      * than processor nodes. Ugh.
	      */
	     int node;
	     Sim_Warning("*** Restoring disk ctrls info from old ckpt ***\n");
	     ASSERT(cptd->mode == CPT_RESTORE);
	     for (node = 0; node < nc; node++)
	       NUM_DISK_CONTROLLERS(machNo, node) = 1;
	     NUM_UNITS_PER_CONTROLLER(machNo) = DEV_DISK_MAX_UNIT;
	   } else {
	     /* new checkpoint code: save controllers/node, units/controller */
	     int node;
	     for (node = 0; node < NUM_CPUS(machNo); node++) {
	       Simcpt_CptParamInt(cptd, "NumDiskControllers",
				  machNo, node,
				  &NUM_DISK_CONTROLLERS(machNo, node));
	     }
	     Simcpt_CptParamInt(cptd, "NumUnitsPerController",
				machNo, NO_INDEX,
				&NUM_UNITS_PER_CONTROLLER(machNo));
 
	   }
	 } 
         Simcpt_CptParamInt(cptd, "NumClocks", machNo, NO_INDEX,
                            &(NUM_CLOCKS(machNo)));
         if (cptd->mode == CPT_RESTORE) {
            MEM_SIZE_SPECIFIED(machNo) = MEM_SIZE(machNo) / (1024 * 1024);
         }
      }   
      
      Simcpt_CptString(cptd, "EthersimHostname", NO_INDEX, NO_INDEX, 
                       &EthersimHostname);
      Simcpt_CptString(cptd, "EtherAddress", NO_INDEX, NO_INDEX,
                       &EtherAddress);
      
   } else if (cptVersion.ver == 3) {

      if ((cptd->mode == CPT_SAVE) && (NUM_MACHINES > 1)) {
         CPUWarning ("WARNING: Checkpoint to ver. 3 format will only save machine 0\n");
      }     
      if (cptd->mode == CPT_RESTORE) {
         NUM_MACHINES = 1;
      }
      Simcpt_CptParamInt(cptd, "MemSize", NO_INDEX, NO_INDEX, &(MEM_SIZE(0)));
      Simcpt_CptParamInt(cptd, "NumCPUs", NO_INDEX, NO_INDEX, &(NUM_CPUS(0)));
      Simcpt_CptString(cptd, "EthersimHostname", NO_INDEX, NO_INDEX, 
                       &EthersimHostname);
      Simcpt_CptString(cptd, "EtherAddress", NO_INDEX, NO_INDEX, &EtherAddress);
      if (cptd->mode == CPT_RESTORE) {
         MEM_SIZE_SPECIFIED(0) = MEM_SIZE(0) / (1024 * 1024);
      }
   } else {
     /* Unknown checkpoint version */
      
      CPUWarning("ERROR: Can't handle checkpoints of version %d.%d\n",
                 cptVersion.ver, cptVersion.sub);
      ASSERT(0);
   }

   /* Do console checkpointing */
   sim_console_ckpt(cptd);

   return 0;
}


static int
TclCheckpointCB(CptDescriptor *cptd)
{
  if (cptd->mode == CPT_RESTORE) TclRestoreCheckpoint(cptName);
  else                           TclDoCheckpoint(cptName);
  return 0;
}



#ifdef sun
#include <sys/types.h>
#include <netinet/in.h>
#include <arpa/inet.h>

int
inet_aton(char *cp, struct in_addr *pin)
{
   struct hostent *hp;

   hp = gethostbyname(cp);

   if (hp == NULL) return 0;
   
   bcopy(hp->h_addr_list[0],pin, sizeof(*pin));

   return 1;
}

#endif