/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/*****************************************************************
 * perfectmem.c
 *
 * Author: $Author: blythe $
 * Date:   $Date: 2002/05/29 01:09:11 $
 *****************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include <time.h>
#include "memsys.h"
#include "sim.h"
#include "sim_error.h"
#include "simutil.h"
#if 0
#include "mipsy.h"
#include "cpu_state.h"
#endif
#include "scache.h"
#include "eventcallback.h"
#include "cpu_interface.h"
#include "machine_params.h"
#include "arch_specifics.h"

#ifdef SOLO
#include "solo_page.h"
#define DATA_ADDR(_m, _pa) SoloGetMemoryAddr(SoloDecompressAddr(0,_pa))
#else
#define DATA_ADDR(_m, _pa) PHYS_TO_MEMADDR(_m, _pa)
#endif

static Result PerfectMemCmd(int cpunum, int cmd, PA paddr,
                            int transId,  PA replacedPaddr, int writeback, 
                            byte *data);
static void PerfectMemDumpStats(void);
static void PerfectMemDone(void);
static void PerfectMemStatus(void);


struct PerfMemStats {
   SimCounter gets; 
   SimCounter igets;
   SimCounter getxs;
   SimCounter uncwrites;
   SimCounter uncaccwrites;
   SimCounter uncreads;
   SimCounter upgrades;
   SimCounter invalidates;
   SimCounter sharingwritebacks;
   SimCounter invalwritebacks;
   SimCounter memreads;
   SimCounter memwrites;
   SimCounter naks;
   SimCounter invalHist[SIM_MAXCPUS];
} perfStats[SIM_MAXCPUS];



#define MAX_OUTSTANDING (SIM_MAXCPUS*MEMSYS_MAX_OUTSTANDING)

static int DoInvalidates(int cpunum, int transId, PA paddr, int mode);
static Result DoMemRequest(int cpunum, int transId, PA paddr, 
                         int mode, byte *data, int len);
static Result DoUncachedRequest(int cpunum, int transId, PA paddr, 
                              uint mcmd, byte *data, int len);

static void InitStats(void);




/*****************************************************************
 * remap region support 
 *****************************************************************/

static PA backmapMask;
static PA nodeaddrMask;

static void
PerfUpdateBackmapMask(void)
{
   /* the backmapMask is an optimization that summarizes all the enabled
    * remap masks; it has ones in any bit position which, if set, means
    * this physical address could not be the target of a remap on any
    * CPU.
    *
    * nodeaddrMask masks out the node id bits.
    */

   int i;
   backmapMask = nodeaddrMask;
   for (i=0; i<TOTAL_CPUS; i++) {
      if (remapVec->RemapEnable[i]) {
	 backmapMask &= remapVec->RemapMask[i];
      }
   }
}

static void
PerfInitRemap(void)
{
   int i, machine;

   /* We initialize backmapMask to all ones except for the
    * bits that might be set in the node id field
    */

   nodeaddrMask = ~0;
   for (machine=0; machine<NUM_MACHINES; machine++) {
       for (i=0; i<NUM_CPUS(machine); i++) {
           if (!remapVec->NodeAddrInitialized) {
#ifdef TORNADO
              int m = machine;
              remapVec->NodeAddr[FIRST_CPU(machine)+i] =
                 (i*NUM_MEMORIES(m)/NUM_CPUS(m)) *
                 (MEM_SIZE(m) / NUM_CPUS(m));
              CPUWarning("perfectmem: nodeaddr for %d/%d is %lx\n",
                         i, FIRST_CPU(machine)+i,
                         (unsigned long)(remapVec->NodeAddr[FIRST_CPU(machine)+i]));
#elif defined(SIM_ORIGIN)
              remapVec->NodeAddr[FIRST_CPU(machine)+i] =
                 MEMADDR_TO_PHYS(machine, SIM_MEM_ADDR(machine) + 
                                 (i/2) * 2 * (MEM_SIZE(machine) / NUM_CPUS(machine)));

#else
              remapVec->NodeAddr[FIRST_CPU(machine)+i] =
                 MEMADDR_TO_PHYS(machine, SIM_MEM_ADDR(machine) + 
                                 i * (MEM_SIZE(machine) / NUM_CPUS(machine)));
#endif
              
           }
           nodeaddrMask &= ~remapVec->NodeAddr[FIRST_CPU(machine)+i];
       }
   }
   remapVec->NodeAddrInitialized = 1;

   /* now zero out the low bits of the backmapmask */
   PerfUpdateBackmapMask();
}

static void
PerfSetRemap(int cpunum, PA mask)
{
   remapVec->RemapMask[cpunum] = mask;
   PerfUpdateBackmapMask();
}

static void
PerfControlRemap(int cpunum, int isEnabled)
{
   remapVec->RemapEnable[cpunum] = isEnabled;
   PerfUpdateBackmapMask();
}

static void
PerfDrain(void)
{
}

static PA
PerfGetNodeAddress(int cpunum)
{
   return remapVec->NodeAddr[cpunum];
}

#define BACKMAP_PADDR(paddr,cpunum)		                   \
   (((paddr & backmapMask)			                   \
     || !remapVec->RemapEnable[cpunum]                             \
     || ((paddr & remapVec->RemapMask[cpunum]) != remapVec->NodeAddr[cpunum])) \
    ? paddr : (paddr - remapVec->NodeAddr[cpunum]))


/*****************************************************************
 * MemsysInit
 *****************************************************************/


/*****************************************************************
 * PerfectMemInit
 *****************************************************************/
void
PerfectMemInit(void)
{
   memsysVec.type = PERFECTMEM;
   memsysVec.MemsysCmd = PerfectMemCmd;
   memsysVec.MemsysDumpStats = PerfectMemDumpStats;
   memsysVec.MemsysDone = PerfectMemDone;
   memsysVec.MemsysStatus = PerfectMemStatus;
   memsysVec.MemsysSetRemap = PerfSetRemap;
   memsysVec.MemsysControlRemap = PerfControlRemap;
   memsysVec.MemsysGetNodeAddress = PerfGetNodeAddress;
   memsysVec.MemsysDrain = PerfDrain;

   /* For now, only allow zero-latency memory */
   memsysVec.NoMemoryDelay = 1;
   if (PERFECTMEM_LATENCY != 0) {
      CPUError("Nonzero fixed memory latency not yet supported\n");
   }
   CPUPrint("MEMSYS - Perfect: %d pclock access time\n",
            PERFECTMEM_LATENCY);

   bzero((char *) perfStats, sizeof(perfStats));
   InitStats();
   PerfInitRemap();
}

/*****************************************************************
 * PerfectMemCmd 
 *****************************************************************/
static Result
PerfectMemCmd(int cpunum, int cmd, PA addr, int transId, 
              PA replacedPaddr, int writeback, byte *data)
{
   int dmalen;
#ifndef SOLO
   addr = REMAP_PADDR(addr, cpunum);
   replacedPaddr = REMAP_PADDR(replacedPaddr, cpunum);
#endif

#ifdef DEBUG
   CPUPrint("MEM: cpu %d, cmd %d, transId %d, addr %08x, replace %08x, "
            "wb %d, data %08x\n",
            cpunum, cmd, transId, addr, replacedPaddr, writeback, data);
#endif

   if (cmd == MEMSYS_SYNC) {
      return SUCCESS;
   } 
   if (writeback && (replacedPaddr != MEMSYS_NOADDR)) {
      ASSERT(!(cmd & MEMSYS_DMAFLAVOR));
#ifdef DATA_HANDLING
      bcopy(data, DATA_ADDR(M_FROM_CPU(cpunum), replacedPaddr),
            SCACHE_LINE_SIZE);
#ifdef DEBUG
      CPUPrint("MEM: Writeback of %08x from %08x to %08x\n",
               replacedPaddr, data, DATA_ADDR(M_FROM_CPU(cpunum),
                                              replacedPaddr));
#endif
#endif
   }
   /* Handle special case: a GET with transId -1 indicates
    * a writeback or repl hint without the associated GET (due
    * to a CACHE instruction executed in the processor)
    */
   if (((cmd & MEMSYS_CMDMASK) == MEMSYS_GET) && (transId == -1) &&
       !(cmd & MEMSYS_DMAFLAVOR)) {
      return SUCCESS;
   }
   if (addr == MEMSYS_NOADDR) {
      /*
       * Ignore writebacks and replacement hints.
       */
      if (writeback) perfStats[cpunum].memwrites++;
      return SUCCESS;
   }
   if( cmd & MEMSYS_DMAFLAVOR ) {
      /* DMA command. This is not issued by any particular CPU
       * and does not unstall the CPU. CacheCmdDone must therefore not
       * be called 
       */
      /* writeback is the length */
      ASSERT( transId < 0 );
      dmalen = writeback; 
   } else { 
      ASSERT( transId >= 0);
      dmalen = 0;
   }
   
   switch (cmd & MEMSYS_CMDMASK) {
   case MEMSYS_GET:
      if( cpunum >= 0) {
         perfStats[cpunum].gets++;    
         if (cmd & MEMSYS_IFFLAVOR) 
            perfStats[cpunum].igets++;
      }
      return DoMemRequest(cpunum, transId, addr, MEMSYS_SHARED,data,dmalen);

   case MEMSYS_GETX:
      if( cpunum>=0 ) 
         perfStats[cpunum].getxs++;
      return DoMemRequest(cpunum, transId, addr, MEMSYS_EXCLUSIVE,data,dmalen);
      
   case MEMSYS_UPGRADE:
      if( cpunum >= 0 )
         perfStats[cpunum].upgrades++;
      return DoMemRequest(cpunum, transId, addr, MEMSYS_EXCLUSIVE,data,dmalen);

   case MEMSYS_UNCWRITE:
      perfStats[cpunum].uncwrites++;
      return DoUncachedRequest(cpunum, transId, addr, 
                               MEMSYS_UNCWRITE, data, writeback);

   case MEMSYS_UNCWRITE_ACCELERATED:
      perfStats[cpunum].uncaccwrites++;
      return DoUncachedRequest(cpunum, transId, addr, 
                               MEMSYS_UNCWRITE_ACCELERATED, data, writeback);

   case MEMSYS_UNCREAD:
      perfStats[cpunum].uncreads++;
      return DoUncachedRequest(cpunum, transId, addr, 
                               MEMSYS_UNCREAD, data, writeback);

   default:
      CPUError("perfectmem_interface.c: Bad memsys command\n");
      break;
   }
   
   return FAILURE;   /* notreached */
}

static Result
DoMemRequest(int cpunum, int transId, PA paddr, int mode, byte *data, int dmalen)
{
   int machine = M_FROM_CPU(cpunum);
   int result = DoInvalidates(cpunum, transId, paddr, mode);      
   if( dmalen ) { 
      if( mode & MEMSYS_EXCLUSIVE ) {
#ifdef DEBUG
         CPUPrint("MEM: DMA write, copying %08x from %08x to %08x\n",
                  paddr, data, DATA_ADDR(machine, paddr));
#endif
         bcopy(data,DATA_ADDR(machine, paddr),dmalen);
      } else { 
#ifdef DEBUG
         CPUPrint("MEM: DMA read, copying %08x from %08x to %08x\n",
                  paddr, DATA_ADDR(machine, paddr), data);
#endif
         bcopy(DATA_ADDR(machine, paddr),data,dmalen);
      }
   } else {
#ifdef DATA_HANDLING
#ifdef DEBUG
      CPUPrint("MEM: Memory request, copying %08x from %08x to %08x\n",
               paddr, DATA_ADDR(machine, paddr), data);
#endif
      bcopy(DATA_ADDR(machine, paddr),data,dmalen);
#endif
   }
   CacheCmdDone(cpunum, transId, mode, MEMSYS_STATUS_SUCCESS, result, data);
   return SUCCESS;
}

static Result
DoUncachedRequest(int cpunum, int transId, PA paddr, uint mcmd, 
                  byte *data, int len)
{
   /* For now, all uncached requests occur immediately */
#ifdef SOLO
   bcopy(data, (char *)paddr, len); 
#else
   Result ret;
#ifdef DEBUG
   CPUPrint("MEM: Uncached %s to address %08x len %d buffer %08x\n",
            (mcmd == MEMSYS_UNCREAD) ? "read" : "write", paddr, len, data);
#endif
   ASSERT(CPUVec.UncachedPIO);
   ret = CPUVec.UncachedPIO(cpunum, paddr, (mcmd == MEMSYS_UNCREAD) ? 1 : 0,
                        len, data);
   ASSERT(ret == SUCCESS);
#endif
   return SUCCESS;
}

/*****************************************************************
 * DoInvalidates
 *****************************************************************/

static int
DoInvalidates(int cpunum, int transId, PA paddr, int mode)
{
   int numinval;
   int result = 0;
   register int i;
   int machine = M_FROM_CPU(cpunum);
   byte *data = (byte*) DATA_ADDR(machine, paddr & ~(SCACHE_LINE_SIZE-1));
   int way;
   
   numinval = 0;
   for (i = FIRST_CPU(machine); i <= LAST_CPU(machine); i++) {
      if (i == cpunum && transId>=0) { 
         /* transId>=0 --> not a DMA request, but a CPU request
          * The requesting CPU is (obviously) not invalidated
          */
         continue;
      }
      if (IsInSCache(i, BACKMAP_PADDR(paddr,i), MEMSYS_SHARED, 
                     (char**)&data, &way)) {
         if (mode == MEMSYS_EXCLUSIVE) {
            int wasDirty;
#ifdef DEBUG
            CPUPrint("MEM: CacheExtract cpu %d addr %08x buffer %08x\n", 
                     i, paddr, data);
#endif
            if (CacheExtract(i, BACKMAP_PADDR(paddr,i), SCACHE_LINE_SIZE, 
                             &wasDirty, data)) {
               perfStats[i].invalidates++;
               numinval++;
               result |= MEMSYS_RESULT_INVALIDATE;
               if (wasDirty) {
                  result |= MEMSYS_RESULT_CACHE;
                  perfStats[i].invalwritebacks++;
               }
            }
         } else {
#ifdef DEBUG
            CPUPrint("MEM: CacheWriteback cpu %d addr %08x buffer %08x\n", 
                     i, paddr, data);
#endif
            if (CacheWriteback(i, BACKMAP_PADDR(paddr,i), SCACHE_LINE_SIZE, data)) {
               perfStats[i].sharingwritebacks++;
               numinval++;
               result |= MEMSYS_RESULT_DOWNGRADE;
               result |= MEMSYS_RESULT_CACHE;
            }
         }
      }
   }
   if (cpunum >= 0) {
      if (numinval == 0) perfStats[cpunum].memreads++;
      if (mode == MEMSYS_EXCLUSIVE) {
         perfStats[cpunum].invalHist[numinval]++;
      }
   }
   if (result == 0) {
      result |= MEMSYS_RESULT_NOTRANSITION;
   }
   if (! (result & MEMSYS_RESULT_CACHE)) {
      result |= MEMSYS_RESULT_MEMORY;
   }
#ifdef DEBUG
   CPUPrint("MEM: request done with result %d\n", result);
#endif
   return result;
}

static struct PerfMemStats lmdstats[SIM_MAXCPUS];

/*****************************************************************
 * PerfectMemDumpStats
 *****************************************************************/
static void 
PerfectMemDumpStats(void)
{
   int i, j;
   double numbytes;
   struct PerfMemStats total, itotal;

   CPUPrint("********* Memory System Stats **********\n");

   bzero((char *) &total, sizeof(total));
   bzero((char *) &itotal, sizeof(itotal));
   numbytes = 0.0;

   for (i = 0; i < TOTAL_CPUS; i++) {          
      numbytes +=  (perfStats[i].gets+perfStats[i].getxs)*(double)SCACHE_LINE_SIZE;
      itotal.gets += (total.gets += perfStats[i].gets) - lmdstats[i].gets;
      itotal.igets += (total.igets += perfStats[i].igets) - lmdstats[i].igets;
      itotal.getxs += (total.getxs += perfStats[i].getxs) - lmdstats[i].getxs;

      itotal.upgrades += 
         (total.upgrades += perfStats[i].upgrades) - lmdstats[i].upgrades;

      itotal.invalidates += 
         (total.invalidates += perfStats[i].invalidates) - lmdstats[i].invalidates;

      itotal.sharingwritebacks += 
         (total.sharingwritebacks += perfStats[i].sharingwritebacks) - 
         lmdstats[i].sharingwritebacks;

      total.uncreads += perfStats[i].uncreads;
      total.uncwrites += perfStats[i].uncwrites;
      total.uncaccwrites += perfStats[i].uncaccwrites;

      for (j = 0; j < TOTAL_CPUS; j++) {
         total.invalHist[j] += perfStats[i].invalHist[j];
      }
      
      itotal.naks += (total.naks += perfStats[i].naks) - lmdstats[i].naks;
      lmdstats[i] = perfStats[i];
   }
   
   CPUPrint("Totals - GETs: %lld (%3.1f%% Ifetch) GETXs: %lld Upgrades: %lld\n",
            (uint64)itotal.gets, (itotal.igets*100.0)/itotal.gets, 
            (uint64)itotal.getxs, (uint64)itotal.upgrades);
   CPUPrint("Totals - Uncached reads: %lld  Uncached writes: %lld  "
            "Uncached accelerated writes: %lld\n",
            (uint64)total.uncreads,
            (uint64)total.uncwrites,
            (uint64)total.uncaccwrites);
   CPUPrint("Totals - Kbytes: %6.2f SharingWritebacks %lld\n",
              numbytes/1000.0, (uint64)itotal.sharingwritebacks);

   for (i = 0; i < TOTAL_CPUS; i++) { 
      CPUPrint("Inval[%d] %lld\n", i, (uint64)total.invalHist[i]);
   }
   
   CPUPrint("Memsys - Invals %d (Avg %4.2f) SharingWritebacks %d NAKs %d\n", 
              itotal.invalidates, 
              itotal.invalidates/(double)(itotal.getxs+itotal.upgrades),
              itotal.sharingwritebacks, itotal.naks);
   
}

static struct PerfMemStats lstats[SIM_MAXCPUS];
/*****************************************************************
 * PerfectMemStatus
 *****************************************************************/
static void
PerfectMemStatus(void)
{
}
#ifdef notdef
static char *
PerfectMemStatus(int cpunum) 
{
   static char buffer[32];

   int i;
   SimCounter memMisses, cacheMisses, invals;
   SimCounter fromCache, lastFromCache, fromMem, lastFromMem;

   memMisses = cacheMisses = invals = 0;

   i = cpunum;
   fromCache = perfStats[i].invalwritebacks + perfStats[i].sharingwritebacks;
   lastFromCache = lstats[i].invalwritebacks + lstats[i].sharingwritebacks;
   fromMem = perfStats[i].memreads;
   lastFromMem = lstats[i].memreads;
   memMisses = (fromMem - lastFromMem);
   cacheMisses = (fromCache - lastFromCache);
   invals = (perfStats[i].invalidates - lstats[i].invalidates);
   invals += (perfStats[i].sharingwritebacks - lstats[i].sharingwritebacks);

   lstats[i] = perfStats[i];

   sprintf(buffer, "M %lld $ %lld I %lld", 
           (uint64)memMisses, 
           (uint64)cacheMisses, 
           (uint64)invals);
   return buffer;
}
#endif
static  void
InitStats(void)
{
   bzero((char *) &lstats, sizeof(lstats));
   bzero((char *) &lmdstats, sizeof(lmdstats));
}

static void
PerfectMemDone(void)
{
   CPUPrint("Done with perfect memory system with latency %d pclocks\n",
              PERFECTMEM_LATENCY);
   PerfectMemDumpStats();
}