/*
 * Copyright (c) 1995, Silicon Graphics, Inc.  All Rights Reserved.
 *
 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
 * the contents of this file may not be disclosed to third parties, copied
 * or duplicated in any form, in whole or in part, without the prior written
 * permission of Silicon Graphics, Inc.
 *
 * RESTRICTED RIGHTS LEGEND:
 * Use, duplication or disclosure by the Government is subject to restrictions
 * as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
 * and Computer Software clause at DFARS 252.227-7013, and/or in similar or
 * successor clauses in the FAR, DOD or NASA FAR Supplement.  Unpublished
 * rights reserved under the Copyright Laws of the United States.
 *
 * Module: dg_utils.c:	Functions of convenience for diag writers.
 */

#include <stdio.h>
#include <stdarg.h>
#include <unistd.h>
#include <sys/types.h>
#ifdef __sgi__
#include <bstring.h>
#endif
#include <stdlib.h>
#include <string.h>
#include <netinet/in.h>

#include "diag.h"
#include "dbg_comm.h"

#define AUTOCC        1

static void WriteCC(unsigned char, unsigned char);

unsigned int pdw_mem;
unsigned int ccreg_address; /* DWORD address of the CCTL reg of the RDRAM
			     being initialized in the application space */
static int InitCCValue(void);
#define	PHYS_TO_K1(x)	((x)|0xA0000000)	/* physical to kseg1 */

int dgListSubTests(TEST_REF *test_refs) 
{
    int testIndex;

    errlog(INFO, "Available Subtests for %s:", ideTestName);
    for (testIndex = 0; test_refs[testIndex].num != TEST_NULL; testIndex++) {
	errlog(INFO, "(%d)\t%s", test_refs[testIndex].num, 
	  test_refs[testIndex].name);
    }
}

#define MANUFACTURE_NEC 0x00000500
#define MANUFACTURE_TOSHIBA 0x00000200
#define NEC_RELEASE_C2

#ifdef NEC_RELEASE_C2
/* NEC Rev C2 mode enable/disable */
#define RDRAM_ENABLE  0xc2000000
#define RDRAM_DISABLE 0xc0000000
#else
/* Non NEC Rev C2 mode enable/disable */
#define RDRAM_ENABLE  0xc6000000
#define RDRAM_DISABLE 0xc4000000
#endif


int
dgInitRdram(void) {
    unsigned int read_data;
    unsigned int read_data1;
    unsigned int next_device;
    unsigned int next_id;
    unsigned int next_reg;
    unsigned int next_1_id;
    unsigned int next_1_mem;
    unsigned int next_1_reg;
    unsigned int next_2_id;
    unsigned int next_2_reg;
    unsigned int next_2_mem;
    unsigned int device_type[8];
    unsigned int cc_value[8];
    unsigned int reg_step;
    unsigned int reg_max;
    unsigned int multibank;
    unsigned int cc;
    int i;


    /* Check if RI was previously initialized by reading a register that
     *  must be non-zero if the RDRAM was configured.
     */
    errlog(DEBUG, "Initializing RDRAM");
    dgReadWord(0x0470000c, &read_data);
    if (read_data) {
	/* the RI has already been initialized */
	if (dgIORevision == 1) {
	    /* reset of initialized RI not supported */
	    return 0;
	} else {
	    /* reset RI to its power on state */
	    dgWriteWord(0x04700000, 0x0000000e);
	    dgWriteWord(0x04700004, 0x00000000);
	    dgWriteWord(0x0470000c, 0x00000000);
	    dgWriteWord(0x04700010, 0x00000000);
	    dgWriteWord(0x04700014, 0x0000000f);
	    dgWriteWord(0x04700018, 0x00000000);
	    dgWriteWord(0x0470001c, 0x00000000);
	}
    }

    /* write current control */
    if (dgIORevision == 1) 
	    dgWriteWord(0x04700004, 0x00000010);
    else
	    dgWriteWord(0x04700004, 0x00000040);

    /* delay 32 cycles for current control */
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);

    /* load current control */
    dgWriteWord(0x04700008, 0x00000000);

    /* load select register */
    dgWriteWord(0x0470000c, 0x00000014);

    /* enable RDRAM reset mode */
    dgWriteWord(0x04700000, 0x00000000);

    /* delay 80 cycles for RDRAM reset */
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);
    dgWriteWord(0x04300000, 0x00000000);

    /* enable standby mode */
    dgWriteWord(0x04700000, 0x0000000e);

    /* enable MI init mode */
    dgWriteWord(0x04300000, 0x0000010f);

    /* write RDRAM Delay register */
    dgWriteWord(0x03f80008, 0x18082838);

    /* write RDRAM RefRow register */
    dgWriteWord(0x03f80014, 0x00000000);

    /* Move all RDRAMs to the top of the address space */
    dgWriteWord(0x03f80004, 0x80000000);

    next_id = 0;
    next_reg = 0x03f00000;
    next_1_id = 0;
    next_1_reg = 0x03f00000;
    next_1_mem = 0;
    next_2_id = 0;
    next_2_reg = 0x03f00000;
    next_2_mem = 0;
    multibank = 0;
    pdw_mem = 0;

    if (dgIORevision == 1) {
	reg_step = 0x00000200;
	reg_max = 0x03f04000;
    } else {
	reg_step = 0x00000400;
	reg_max = 0x03f08000;
    }

    for (next_device = 0; next_device < 8; next_device++) {
	/* move the next RDRAM to the next 2 MByte slot */
	dgWriteWord(reg_max + 0x4, next_id);

	/* enable the RDRAM */
	ccreg_address = next_reg + 0xc;
	cc = InitCCValue();
	if (cc == 0)
		break;
	cc_value[next_device] = cc;
  
	/* determine the RDRAM size */
	dgWriteWord(0x04300000, 0x00002000);
	dgReadWord(next_reg + 0x0, &read_data);
	device_type[next_device] = read_data & 0xf0ff0000;
	dgWriteWord(0x04300000, 0x00001000);
  

	switch (device_type[next_device]) {
	case 0xb0090000 :
	    pdw_mem = pdw_mem + 0x00100000;
            errlog(DEBUG, "Found 1 Mbyte RDRAM");
	    break;

	case 0xb0190000 :
	    next_1_id = next_1_id + 0x08000000;
	    next_1_reg = next_1_reg + (reg_step * 2);
	    next_1_mem = next_1_mem + 0x00200000;
	    pdw_mem = pdw_mem + 0x00200000;
            multibank = (multibank << 1) + 1;
            errlog(DEBUG, "Found 2 Mbyte RDRAM");
	    break;

	default :
	    errlog(ERR_SEVERE, "Unsupported RDRAM size = 0x%x",
		   device_type[next_device]);
	}

	dgWriteWord(0x04300000, 0x00002000);
	dgReadWord(next_reg + 0x24, &read_data);
	dgReadWord(next_reg + 0x0, &read_data1);
	dgWriteWord(0x04300000, 0x00001000);
  
	if (((read_data & 0x0000ffff) == MANUFACTURE_NEC)
	    && ((read_data1 & 0x01000000) == 0)) {
	    errlog(DEBUG, "NEC RDRAM", read_data);
	    dgWriteWord(next_reg + 0x18, 0x101c0a04);
	} else if ((read_data & 0x0000ffff) == MANUFACTURE_TOSHIBA) {
	    errlog(DEBUG, "Toshiba RDRAM", read_data);
	    dgWriteWord(next_reg + 0x18, 0x080c1204);
	} else {
	    errlog(DEBUG, "Unknown RDRAM - 0x%x", read_data);
	    errlog(DEBUG, "Using Toshiba RAS interval", read_data);
	    dgWriteWord(next_reg + 0x18, 0x080c1204);
	}

	next_id = next_id + 0x08000000;
	next_reg = next_reg + (reg_step * 2);
    }

    /* Reinitialize all the RDRAMs */
    dgWriteWord(0x03f8000c, RDRAM_DISABLE);
    dgWriteWord(0x03f80004, 0x80000000);
  
    /* Group the RDRAMs in 1 Mbyte and 2 Mbyte blocks */
    for (i = 0; i < next_device; i++) {
	switch (device_type[i]) {
	case 0xb0090000 :
	    /* Move the RDRAM to the next 1 Mbyte slot */
	    dgWriteWord(reg_max + 0x4, next_1_id);
	    ccreg_address = next_1_reg + 0xc;
            WriteCC(cc_value[i], AUTOCC);  /* Write the final auto CC value */
    
	    /* Tickle the RDRAM */
	    dgReadWord(next_1_mem + 0x00000, &read_data);
	    dgReadWord(next_1_mem + 0x80000, &read_data);
	    dgReadWord(next_1_mem + 0x00000, &read_data);
	    dgReadWord(next_1_mem + 0x80000, &read_data);
    
	    next_1_id = next_1_id + 0x04000000;
	    next_1_reg = next_1_reg + reg_step;
	    next_1_mem = next_1_mem + 0x00100000;
	    break;
    
	case 0xb0190000 :
	    /* Move the RDRAM to the next 2 Mbyte slot */
	    dgWriteWord(reg_max + 0x4, next_2_id);
	    ccreg_address = next_2_reg + 0xc;
            WriteCC(cc_value[i], AUTOCC);  /* Write the final auto CC value */
    
	    /* Tickle the RDRAM */
	    dgReadWord(next_2_mem + 0x000000, &read_data);
	    dgReadWord(next_2_mem + 0x080000, &read_data);
	    dgReadWord(next_2_mem + 0x100000, &read_data);
	    dgReadWord(next_2_mem + 0x180000, &read_data);
	    dgReadWord(next_2_mem + 0x000000, &read_data);
	    dgReadWord(next_2_mem + 0x080000, &read_data);
	    dgReadWord(next_2_mem + 0x100000, &read_data);
	    dgReadWord(next_2_mem + 0x180000, &read_data);
    
	    next_2_id = next_2_id + 0x08000000;
	    next_2_reg = next_2_reg + (reg_step * 2);
	    next_2_mem = next_2_mem + 0x00200000;
	    break;
    
	default :
	    errlog(ERR_SEVERE, "Device_type table corrupt - %x",
		   device_type[i]);
	    break;
	}
    }

    /* enable refresh */
    dgWriteWord(0x04700010, 0x63634 | (multibank << 19));

    /* display spiffy message */
    errlog(INFO, "%d Mbytes RDRAM ready", next_1_mem / 0x100000);
    return 0;
}


int
dgTestReg(unsigned int address,
	  unsigned int write_data,
	  unsigned int expect_data) {

  unsigned int read_data;

  if (dgWriteWord(address, write_data)) return(1);
  if (dgReadWord(address, &read_data)) return(1);
  if (read_data != expect_data) {
    errlog(ERR_SEVERE,
	   "data miscompare - ad = %08x, wr = %08x, rd = %08x, ex = %08x",
	   address, write_data, read_data, expect_data);
    return(1);
  } else {
    errlog(DEBUG,
	   "compare - ad = %08x, wr = %08x, rd = %08x, ex = %08x",
	   address, write_data, read_data, expect_data);
    return(0);
  }
}

int
dgTestRegMsk(unsigned int address,
          unsigned int write_data,
          unsigned int expect_data,
          unsigned int mask) {

  unsigned int read_data;

  if (dgWriteWord(address, write_data)) return(1);
  if (dgReadWord(address, &read_data)) return(1);
  read_data &= mask;
  expect_data &= mask;
  if (read_data != expect_data) {
    errlog(ERR_SEVERE,
           "data miscompare - ad = %08x, wr = %08x, rd = %08x, ex = %08x",
           address, write_data, read_data, expect_data);
    return(1);
  } else {
    errlog(DEBUG,
           "compare - ad = %08x, wr = %08x, rd = %08x, ex = %08x",
           address, write_data, read_data, expect_data);
    return(0);
  }
}

int
dgRdTestWordMsk(unsigned int address,
                unsigned int expect_data,
                unsigned int mask) {

  unsigned int read_data;

  if (dgReadWord(address, &read_data)) return(1);
  read_data &= mask;
  expect_data &= mask;
  if (read_data != expect_data) {
    errlog(ERR_SEVERE,
           "data miscompare - ad = %08x, rd = %08x, ex = %08x",
           address, read_data, expect_data);
    return(1);
  } else {
    errlog(DEBUG,
           "compare - ad = %08x, rd = %08x, ex = %08x",
           address, read_data, expect_data);
    return(0);
  }
}

void
dgWait(char *fmt, ...)
{
  char buf[1024];
  va_list args;

  /* print the message */
  va_start(args, fmt);
  printf("WAIT:   ");
  vprintf(fmt, args);
  va_end(args);

  if (isatty(0)) {
    /* only wait if reading from a tty */
    printf(" (press Enter to continue) ");
#ifdef __sgi__
    gets(buf);
#else
    fgets(buf, sizeof buf, stdin);
#endif
  }
  else {
    printf("\n");
  }
}


/******************************************************************************/
/* Toggle the interrupt line for scope trace                                  */
/******************************************************************************/
 
void
dgTrigger(void)
{
  dgWriteWord(0x0430000c, 0x00000002); /* enable sp interrupt */
  dgWriteWord(0x04040010, 0x00000010); /* set sp interrupt */
  dgWriteWord(0x04040010, 0x00000008); /* clear sp interrupt */
  }


int
dgCompareWord(unsigned int address,
	      unsigned int expect_data)
{
  unsigned int read_data;

  dgReadWord(address, &read_data);
  if (expect_data != read_data) {
    errlog(ERR_SEVERE,
	   "data miscompare - ad = %08x, wr = %08x, rd = %08x",
	   address, expect_data, read_data);
    return 1;
  }
  return 0;
}



/* video formats */
#define VI_NTSC_LPN1 0
#define VI_NTSC_LPF1 1
#define VI_NTSC_LAN1 2
#define VI_NTSC_LAF1 3
#define VI_NTSC_LPN2 4
#define VI_NTSC_LPF2 5
#define VI_NTSC_LAN2 6
#define VI_NTSC_LAF2 7
#define VI_NTSC_HPN1 8
#define VI_NTSC_HPF1 9
#define VI_NTSC_HAN1 10
#define VI_NTSC_HAF1 11
#define VI_NTSC_HPN2 12
#define VI_NTSC_HPF2 13

#define VI_PAL_LPN1  14
#define VI_PAL_LPF1  15
#define VI_PAL_LAN1  16
#define VI_PAL_LAF1  17
#define VI_PAL_LPN2  18
#define VI_PAL_LPF2  19
#define VI_PAL_LAN2  20
#define VI_PAL_LAF2  21
#define VI_PAL_HPN1  22
#define VI_PAL_HPF1  23
#define VI_PAL_HAN1  24
#define VI_PAL_HAF1  25
#define VI_PAL_HPN2  26
#define VI_PAL_HPF2  27


int
dgEnableVideo(unsigned int start_address,
	      int mode)
{
  int error_count = 0;

  /* program the VI and enable */
  dgWriteWord(0x04400004, start_address);
  dgWriteWord(0x0440000c, 0x000003ff);
  dgWriteWord(0x04400010, 0x00000000);

  /* set ntsc/pal parameters */
  switch (mode) {
  case VI_NTSC_LPN1:
  case VI_NTSC_LPF1:
  case VI_NTSC_LAN1:
  case VI_NTSC_LAF1:
  case VI_NTSC_LPN2:
  case VI_NTSC_LPF2:
  case VI_NTSC_LAN2:
  case VI_NTSC_LAF2:
  case VI_NTSC_HPN1:
  case VI_NTSC_HPF1:
  case VI_NTSC_HAN1:
  case VI_NTSC_HAF1:
  case VI_NTSC_HPN2:
  case VI_NTSC_HPF2:
    dgWriteWord(0x04400014, 0x03e52239);
    dgWriteWord(0x0440001c, 0x00000c15);
    dgWriteWord(0x04400020, 0x0c150c15);
    dgWriteWord(0x04400024, 0x007402f4);
    dgWriteWord(0x04400028, 0x00290209);
    dgWriteWord(0x0440002c, 0x00110209);
    break;

  case VI_PAL_LPN1:
  case VI_PAL_LPF1:
  case VI_PAL_LAN1:
  case VI_PAL_LAF1:
  case VI_PAL_LPN2:
  case VI_PAL_LPF2:
  case VI_PAL_LAN2:
  case VI_PAL_LAF2:
  case VI_PAL_HPN1:
  case VI_PAL_HPF1:
  case VI_PAL_HAN1:
  case VI_PAL_HAF1:
  case VI_PAL_HPN2:
  case VI_PAL_HPF2:
    dgWriteWord(0x04400014, 0x0404233a);
    dgWriteWord(0x0440001c, 0x00150c69);
    dgWriteWord(0x04400020, 0x0c6f0c6e);
    dgWriteWord(0x04400024, 0x00800300);
    dgWriteWord(0x04400028, 0x005b023b);
    dgWriteWord(0x0440002c, 0x000f026d);
    break;
  }

  /* set VI_WIDTH */
  switch (mode) {
  case VI_NTSC_LPN1:
  case VI_NTSC_LPF1:
  case VI_NTSC_LAN1:
  case VI_NTSC_LAF1:
  case VI_NTSC_LPN2:
  case VI_NTSC_LPF2:
  case VI_NTSC_LAN2:
  case VI_NTSC_LAF2:
  case VI_PAL_LPN1:
  case VI_PAL_LPF1:
  case VI_PAL_LAN1:
  case VI_PAL_LAF1:
  case VI_PAL_LPN2:
  case VI_PAL_LPF2:
  case VI_PAL_LAN2:
  case VI_PAL_LAF2:
    dgWriteWord(0x04400008, 0x00000140);
    break;

  case VI_NTSC_HPN1:
  case VI_NTSC_HAN1:
  case VI_NTSC_HPN2:
  case VI_PAL_HPN1:
  case VI_PAL_HAN1:
  case VI_PAL_HPN2:
    dgWriteWord(0x04400008, 0x00000500);
    break;

  case VI_NTSC_HPF1:
  case VI_NTSC_HAF1:
  case VI_NTSC_HPF2:
  case VI_PAL_HPF1:
  case VI_PAL_HAF1:
  case VI_PAL_HPF2:
    dgWriteWord(0x04400008, 0x00000280);
    break;
  }

  /* set VI_V_SYNC */
  switch (mode) {
  case VI_NTSC_LPN1:
  case VI_NTSC_LAN1:
  case VI_NTSC_LPN2:
  case VI_NTSC_LAN2:
    dgWriteWord(0x04400018, 0x0000020b);
    break;

  case VI_NTSC_LPF1:
  case VI_NTSC_LAF1:
  case VI_NTSC_LPF2:
  case VI_NTSC_LAF2:
  case VI_NTSC_HPN1:
  case VI_NTSC_HAN1:
  case VI_NTSC_HPN2:
  case VI_NTSC_HPF1:
  case VI_NTSC_HAF1:
  case VI_NTSC_HPF2:
    dgWriteWord(0x04400018, 0x0000020c);
    break;

  case VI_PAL_LPN1:
  case VI_PAL_LAN1:
  case VI_PAL_LPN2:
  case VI_PAL_LAN2:
    dgWriteWord(0x04400018, 0x0000026f);
    break;

  case VI_PAL_LPF1:
  case VI_PAL_LAF1:
  case VI_PAL_LPF2:
  case VI_PAL_LAF2:
  case VI_PAL_HPN1:
  case VI_PAL_HAN1:
  case VI_PAL_HPN2:
  case VI_PAL_HPF1:
  case VI_PAL_HAF1:
  case VI_PAL_HPF2:
    dgWriteWord(0x04400018, 0x00000270);
    break;
  }

  /* set VI_X_SCALE & VI_Y_SCALE */
  switch (mode) {
  case VI_NTSC_LPN1:
  case VI_NTSC_LAN1:
  case VI_NTSC_LPN2:
  case VI_NTSC_LAN2:
  case VI_PAL_LPN1:
  case VI_PAL_LAN1:
  case VI_PAL_LPN2:
  case VI_PAL_LAN2:
    dgWriteWord(0x04400030, 0x00000200);
    dgWriteWord(0x04400034, 0x00000400);
    break;

  case VI_NTSC_LPF1:
  case VI_NTSC_LAF1:
  case VI_NTSC_LPF2:
  case VI_NTSC_LAF2:
  case VI_PAL_LPF1:
  case VI_PAL_LAF1:
  case VI_PAL_LPF2:
  case VI_PAL_LAF2:
    dgWriteWord(0x04400030, 0x00000200);
    dgWriteWord(0x04400034, 0x01000400);
    break;

  case VI_NTSC_HPN1:
  case VI_NTSC_HAN1:
  case VI_NTSC_HPN2:
  case VI_PAL_HPN1:
  case VI_PAL_HAN1:
  case VI_PAL_HPN2:
    dgWriteWord(0x04400030, 0x00000400);
    dgWriteWord(0x04400034, 0x00000400);
    break;

  case VI_NTSC_HPF1:
  case VI_NTSC_HAF1:
  case VI_NTSC_HPF2:
  case VI_PAL_HPF1:
  case VI_PAL_HAF1:
  case VI_PAL_HPF2:
    dgWriteWord(0x04400030, 0x00000400);
    dgWriteWord(0x04400034, 0x02000800);
    break;
  }

  /* set VI_CTRL */
  switch (mode) {
  case VI_NTSC_LPN1:
    /* ntsc, 320 x 240, 16 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003202);
    break;

  case VI_NTSC_LPF1:
    /* ntsc, 320 x 240, 16 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003242);
    break;

  case VI_NTSC_LAN1:
    /* ntsc, 320 x 240, 16 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003112);
    break;

  case VI_NTSC_LAF1:
    /* ntsc, 320 x 240, 16 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003152);
    break;

  case VI_NTSC_LPN2:
    /* ntsc, 320 x 240, 32 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003303);
    break;

  case VI_NTSC_LPF2:
    /* ntsc, 320 x 240, 32 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003243);
    break;

  case VI_NTSC_LAN2:
    /* ntsc, 320 x 240, 32 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003013);
    break;

  case VI_NTSC_LAF2:
    /* ntsc, 320 x 240, 32 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003053);
    break;

  case VI_NTSC_HPN1:
    /* ntsc, 640 x 480, 16 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003342);
    break;

  case VI_NTSC_HPF1:
    /* ntsc, 640 x 480, 16 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003242);
    break;

  case VI_NTSC_HAN1:
    /* ntsc, 640 x 480, 16 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003052);
    break;

  case VI_NTSC_HAF1:
    /* ntsc, 640 x 480, 16 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003052);
    break;

  case VI_NTSC_HPN2:
    /* ntsc, 640 x 480, 32 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003343);
    break;

  case VI_NTSC_HPF2:
    /* ntsc, 640 x 480, 32 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003243);
    break;

  case VI_PAL_LPN1:
    /* pal, 320 x 240, 16 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003302);
    break;

  case VI_PAL_LPF1:
    /* pal, 320 x 240, 16 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003242);
    break;

  case VI_PAL_LAN1:
    /* pal, 320 x 240, 16 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003112);
    break;

  case VI_PAL_LAF1:
    /* pal, 320 x 240, 16 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003152);
    break;

  case VI_PAL_LPN2:
    /* pal, 320 x 240, 32 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003303);
    break;

  case VI_PAL_LPF2:
    /* pal, 320 x 240, 32 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003243);
    break;

  case VI_PAL_LAN2:
    /* pal, 320 x 240, 32 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003013);
    break;

  case VI_PAL_LAF2:
    /* pal, 320 x 240, 32 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003053);
    break;

  case VI_PAL_HPN1:
    /* pal, 640 x 480, 16 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003342);
    break;

  case VI_PAL_HPF1:
    /* pal, 640 x 480, 16 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003242);
    break;

  case VI_PAL_HAN1:
    /* pal, 640 x 480, 16 bit, anti-aliased, non-interlaced */
    dgWriteWord(0x04400000, 0x00003052);
    break;

  case VI_PAL_HAF1:
    /* pal, 640 x 480, 16 bit, anti-aliased, interlaced */
    dgWriteWord(0x04400000, 0x00003052);
    break;

  case VI_PAL_HPN2:
    /* pal, 640 x 480, 32 bit, point-sampled, non-interlaced */
    dgWriteWord(0x04400000, 0x00003343);
    break;

  case VI_PAL_HPF2:
    /* pal, 640 x 480, 32 bit, point-sampled, interlaced */
    dgWriteWord(0x04400000, 0x00003243);
    break;

  default:
    errlog(ERR_SEVERE, "unsupported video mode - %d", mode);
    return 1;
  }
  return 0;
}


/*
    ***************************************************************************
    * Copyright 1995 Rambus Inc., All Rights Reserved                         *
    * CONFIDENTIAL INFORMATION - RAMBUS INC. PROPRIETARY                      *
    *                                                                         *
    * Data contained herein is proprietary information of Rambus Inc.         *
    * which shall be treated confidentially and shall not be furnished to     *
    * third parties or made PUBLIC without prior written permission by        *
    * Rambus Inc. Rambus Inc. does not convey any license under its           *
    * patent, copyright or maskwork rights or any rights of others.           *
    *                                                                         *
    * Data contained herein is preliminary. Rambus Inc. makes no warranties,  *
    * expressed or implied, of functionality or suitability for any purpose.  *
    * Rambus Inc. assumes no obligation to correct any errors contained       *
    * herein or to advise any user of this text of any correction if such be  *
    * made.                                                                   *
    ***************************************************************************
*     July 17, 1995
*     Changes for assembly optimization: September 21, 1995
*/


/*
 * Notation:
 *  DWORD - a 32-bit integer
 *  BYTE  - a 8-bit integer
 */


/*
 * The following parameter and function definitions are application
 * dependent. They should be mapped to the appropriate initialization
 * routines for the application.
 */
 

/* 
 * The following code is an implementation of the auto current control
 * algorithm.
 */

#define DERWMASK              0x02000000
#define ASRWMASK              0x04000000
#define X2RWMASK              0x40000000
#define CERWMASK              0x80000000
#define C0RMASK               0x00000040
#define C1RMASK               0x00004000
#define C2RMASK               0x00400000
#define C3RMASK               0x00000080
#define C4RMASK               0x00008000
#define C5RMASK               0x00800000
#define C0WMASK               0x00000001
#define C1WMASK               0x00000002
#define C2WMASK               0x00000004
#define C3WMASK               0x00000008
#define C4WMASK               0x00000010
#define C5WMASK               0x00000020
#define C0SHIFT               6
#define C1SHIFT               13
#define C2SHIFT               20
#define C3SHIFT               4
#define C4SHIFT               11
#define C5SHIFT               18

#define MAXTRYS       10
#define MANUALCC      2
#define CHECKSHIFT    16
#define CCMASK        0x3f 


static int mgi_readoffset = 4;	/* dword offset for read */

void WriteCC(unsigned char b_value, unsigned char b_auto)
{
#ifdef NEC_RELEASE_C2
 unsigned int dw_value = (DERWMASK|X2RWMASK);
#else
 unsigned int dw_value = (DERWMASK|X2RWMASK|ASRWMASK);
#endif

 b_value ^= (CCMASK) ; 

 if(b_auto == AUTOCC)
  {
   dw_value |= CERWMASK ;
  }

 dw_value |= (b_value&C0WMASK)<<C0SHIFT;
 dw_value |= (b_value&C1WMASK)<<C1SHIFT;
 dw_value |= (b_value&C2WMASK)<<C2SHIFT;
 dw_value |= (b_value&C3WMASK)<<C3SHIFT;
 dw_value |= (b_value&C4WMASK)<<C4SHIFT;
 dw_value |= (b_value&C5WMASK)<<C5SHIFT;

 dgWriteWord(ccreg_address, dw_value);

 /*
  * In auto-mode, introduce a delay of 512 (Rambus bus) clocks to ensure
  * that the auto current control circuitry calibrates to the new value
  * Code this as a simple delay loop that delays for about 2048ns.
  */

 if (b_auto == AUTOCC) {
   dgWriteWord(0x04300000, 0x00000000);
  }
 
}


static void ReadCC(unsigned char * b_value)
{
 unsigned int dw_value = 0;
 unsigned int dw_tmp;

	dgWriteWord(0x04300000, 0x00002000);
	dgReadWord(ccreg_address, &dw_value);
	dgWriteWord(0x04300000, 0x00001000);


   dw_tmp = 0;
   dw_tmp |= (dw_value&C0RMASK)>>C0SHIFT;
   dw_tmp |= (dw_value&C1RMASK)>>C1SHIFT;
   dw_tmp |= (dw_value&C2RMASK)>>C2SHIFT;
   dw_tmp |= (dw_value&C3RMASK)>>C3SHIFT;
   dw_tmp |= (dw_value&C4RMASK)>>C4SHIFT;
   dw_tmp |= (dw_value&C5RMASK)>>C5SHIFT;

   *b_value = (unsigned char) dw_tmp ;
}


#define MULT  22
#define MFAC  10
#define NTRY  10
#define BITS   8
#define TRYBITS (NTRY*BITS)

static int ConvertManualToAuto(int i_ccvalue)
{
 int i_readccval = 0;
 int i_minccval = 0;
 int i_delccval = 64*MFAC*TRYBITS;
 unsigned char b_readccval = 0;
 int i_accval;
 int i_dccv;

 for(i_accval = 0; i_accval < 65 ; i_accval++)
  {
   if(i_accval > 63)
    {
	 return(0) ;
	}
   WriteCC(i_accval, AUTOCC);

    /*
     * Now read back the calibrated value. The read of this register is
     * done 2 times and the last value is the one that is used.
     * A "dummy" transaction is required (for NEC Rev D parts) for the
     * calibrated current control value to be loaded for a read.
     */

/* The first ReadCC below is a dummy transaction read: the results of
   the read are not used. In the assembly code, optimize for this case
 */
   ReadCC((unsigned char *)&b_readccval);	/* Dummy transaction */
   
   ReadCC((unsigned char *)&b_readccval);
   i_readccval = (MFAC*TRYBITS)*b_readccval;
   i_dccv = abs(i_readccval-i_ccvalue);
   if(i_dccv < i_delccval)
    {
	 i_delccval = i_dccv;
	 i_minccval = i_accval;
	}
   if(i_readccval>=i_ccvalue)
    break;
  }


 return(((i_minccval+i_accval)/2)) ;

}


static int TestCCValue(int b_value)
{
 int i_passcount = 0;
 int j, k;
 unsigned int dw_value;
 WriteCC(b_value, MANUALCC);

 for(j=0; j < NTRY ; j++)
  {
   dgWriteWord(pdw_mem, 0xffffffff);
   dgWriteWord(pdw_mem, 0xffffffff);
   dgWriteWord(pdw_mem+mgi_readoffset, 0xffffffff);

   dgReadWord(pdw_mem+mgi_readoffset, &dw_value);
   dw_value = (dw_value >>CHECKSHIFT);
     for(k = 0; k < BITS ; k++)
     {
	if((dw_value&0x00000001))
	    i_passcount++;
	dw_value = dw_value>>1;
      }
    }
 return(i_passcount);
}


static int FindCC()
{
 int i_ccvalue = 0;
 int i_prevpass = 0;
 int i_pass = 0;
 int i_sumv = 0;
 int j;
 int i_accvalue;

 for(j = 0; i_prevpass < TRYBITS ; j++)
  {
   if(j > 63)
    {
	 return(0);			/* no memory */
	}
   i_pass = TestCCValue(j);
   if(i_pass > 0)
    {
     i_sumv += j*(i_pass-i_prevpass);
     i_prevpass = i_pass ;
    }
  }
 

 i_ccvalue = MULT*(i_sumv - (TRYBITS/2)) ;
 printf("i_ccvalue %d\n", i_ccvalue);

 /*phase 2 convert manual to auto*/
 i_accvalue = ConvertManualToAuto(i_ccvalue);
 printf("i_accvalue %d\n", i_accvalue);
 return (i_accvalue);
}


/*
 * The "main" routine for initializing auto current control for a single
 * RDRAM. 
 */ 

#define	PASSES	4	/* Number of iterations of algorithm */

static int InitCCValue()

{
  int i, accv, sumccv;
  unsigned char cc = 0;

  sumccv = 0;
  for (i=0; i<PASSES; i++) {
    accv = FindCC();
    sumccv += accv;
  }
  accv = sumccv/PASSES;
  printf("accv %x\n", accv); 
  WriteCC(accv, AUTOCC);  /* Write the final auto CC value */
  ReadCC((unsigned char *)&cc);
  printf("readback cc %d\n", cc); 
  return(accv);

}
#ifdef jean
new_WriteCC()
{
	ccreg_address = 0x03f0000c;
	WriteCC(15, 2);
}
#endif