/**************************************************************************
 *
 * Main file for SI test functions
 *
 * $Revision: 1.2 $
 *
 */

#include <sys/types.h>
#ifdef __sgi__
#include <sys/sbd.h>
#endif
#include <sys/stat.h>
#include <sys/mman.h>
#ifdef __sgi__
#include <sys/sema.h>
#endif
#include <netinet/in.h>

#include <errno.h>
#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <getopt.h>

#include <sys/u64driver.h>
#include <rcp.h>

/*
 * From $ROOT/usr/include/ide, which is installed from $ROOT/PR/diags/include
 */
#include "diag.h"
#include "dbg_comm.h"


/**************************************************************************
 *
 * Main definitions
 *
 */
#define DIR_READ    0   /* Rdram <- device */
#define DIR_WRITE   1   /* Rdram -> device */

#define SI_TEST_BASE    1


/**************************************************************************
 *
 * Function prototypes
 *
 */
static int  testInit();
static int  testDo(TEST_REF *test_ref);
static int  siTestReg(TEST_REF *test_ref);
static int  siTestIo(TEST_REF *test_ref);
static int  siReadController(TEST_REF *test_ref);
static int  siTestDma(TEST_REF *test_ref);
static int  siPollStatus(unsigned int, int);

/* orhpaned function */
static int  siReadRom(TEST_REF *test_ref);

int     siIoWrite(unsigned int, unsigned int);
unsigned int    siIoRead(unsigned int);
int     siDmaCopy(int, unsigned int, unsigned int);
int     siCompare(unsigned int, unsigned int, int);

/**************************************************************************
 *
 * Private global variables
 *
 */
/*
 * Create an array of tests, each of which corresponds to a separate menu
 * item callable from the master ide menu.
 */
static TEST_REF testRefs[] = {
    {"SI register test",    SI_TEST_BASE+0, siTestReg},
    {"SI I/O read/write test",  SI_TEST_BASE+1, siTestIo},
    {"END OF TESTS",0,0}
};

/* orphaned test
{"READ SI ROM Data",    SI_TEST_BASE+3, siReadRom},
{"SI DMA test",         SI_TEST_BASE+2, siTestDma},
{"Game Controllers Bus Test",  SI_TEST_BASE+2, siReadController},
*/
static int Initialize  = 1;
static int NumFailures = 0;
static int Failed      = 0;


/**************************************************************************
 *
 * Functions
 *
 */

/*
 * diagnostic entry point:
 *
 * Each separately invokable ide diagnostic command corresponds to an
 * independent ".c" module; the entry point herein must match
 * the test name as specified in the rdpcmd.awk script.  These command
 * names correspond to the names you see from the ide menu.  For this
 * module, there will be an ide command "si" (until this
 * silly module is retired, that is).
 */
int siTestEntry()
{
    int c;
    int testNum;

    Initialize  = 1;
    Failed  = 0;
    NumFailures = 0;

    /*
     * Sample of how to parse command line args received from ide
     */
    while ((c = getopt(pGlobalComm->argc, pGlobalComm->argv, "ht:I")) != EOF) {
    switch(c) {
        case 'h':
        /*
         * Print out the available subtests, then return without
         * invoking any subtests (which is done by calling diaginit()).
         */
        dgListSubTests(testRefs);
        return(0);
        break;
        case 't':
        testNum = atoi(optarg);
        pGlobalComm->entryNum = -(testNum);
        break;
        case 'I':
        Initialize = 0;
        break;
        default:
        printf("weird option character %c = 0x%x\n", c, c);
        break;
        }
    }

    /*
     * IDE will call our one-time initialization function testInit(),
     * then invoke testDo() for as many tests as we've put into the
     * global test array "testRefs", declared at the top of this module.
     */
    diaginit(testRefs, testInit, testDo);

    if (Failed) {
        errlog(INFO, "... test %s FAILED", ideTestName);
    } else {
    errlog(INFO, "... test %s PASSED", ideTestName);
    }

}  /* siTestEntry */


/**************************************************************************
 * Test init fuction
 */
static int testInit()
{
    errlog(INFO, "Starting test %s ... ", ideTestName);
    return(0);
}  /* testInit */


/**************************************************************************
 * Test caller
 */
static int testDo(TEST_REF *test_ref)
{
    int rc;
    int errorCount;

    errlog(INFO, "--- starting subtest %s (%d)", test_ref->name, test_ref->num);

    /*
     * Reset the target system, if necessary
     * Setup the diagnostic communication link to the target system.
     */
    if (Initialize) {
        errlog(DEBUG, "--- initializing target");
        dgInitComm();
    }

    /*
     * Invoke the actual test from the "TEST_REF" array statically declared
     * as a global within this test module.
     */
    if (errorCount = test_ref->fnc(test_ref)) {
        NumFailures += errorCount;
        Failed = 1;
        errlog(INFO, "--- subtest %s FAILED, %d failures",
            test_ref->name, errorCount);
    } else  {
        errlog(INFO, "--- subtest %s PASSED", test_ref->name);
    }
    return(0);

}  /* testDo */


/**************************************************************************
 *
 * Main SI test functions
 *
 **************************************************************************/

/**************************************************************************
 * Perform SI I/O write/read test
 */
static int
siIoWRTest(unsigned int addr, unsigned int wdata)
{
    unsigned int rdata;

    siIoWrite(addr, wdata);
    rdata = siIoRead(addr);
    if (rdata != wdata) {
        errlog(ERR_SEVERE,
           "data miscompare - ad = %08x, wr = %08x, rd = %08x",
           addr, wdata, rdata);
        return(1);
    }
    else {
        errlog(DEBUG,
           "compare - ad = %08x, wr = %08x, rd = %08x", addr, wdata, rdata);
    }
    return(0);

}  /* siIoWRTest */


/**************************************************************************
 *              REGISTER TESTS
 **************************************************************************/

/* Data table */
static unsigned int regDataTable[] = {
    0x00000000, 0xFFFFFFFF, 0xAAAAAAAA, 0x55555555, 0xDEADBEEF
};
static unsigned int regDataTableSize= sizeof(regDataTable)/sizeof(unsigned int);

int
siTestReg(TEST_REF *test_ref)
{
    int     i;
    int     errorCount = 0;

    /*
     * For each register address, test it with all the pattern data in
     * data table.
     */
    for (i = 0; i < regDataTableSize; i++) {
        if (dgTestReg(SI_DRAM_ADDR_REG, regDataTable[i],
                  (regDataTable[i] & 0x00FFFFFC))) {
            errorCount++;
        }
    }

    return(errorCount);

}  /* siTestReg */


/**************************************************************************
 *              SIO TESTS
 **************************************************************************
 * Perform IO Write/Read from different SI PIF RAM address space
 */
/* Data table */
static unsigned int ioDataTable[] = {
    0x00000000, 0xFFFFFFFF, 0xAAAAAAAA, 0x55555555, 0xA5A5A5A5, 0x5A5A5A5A
};
static unsigned int ioDataTableSize= sizeof(ioDataTable)/sizeof(unsigned int);

int
siTestIo(TEST_REF *test_ref)
{
    int         i, j;
    int         errorCount = 0;

    /*
     * Write/Read PIF RAM (64 bytes == 16 words) with pattern data
     * do not test the status reg at address 1fc007fc, so run
     * only 15 word test
     */
    for (i = 0; i < 15; i++) {
        for (j = 0; j < ioDataTableSize; j++) {
            if (siIoWRTest(PIF_RAM_START+(i*4), ioDataTable[j])) {
                errorCount++;
            }
        }
    }
    /* do an addressing pattern */
    for (i = 0; i < 15; i++) {
            if (siIoWRTest(PIF_RAM_START+(i*4), i)) {
                errorCount++;
        }
    }


    return(errorCount);

}  /* siTestIo */


/**************************************************************************
 *              DMA TESTS
 **************************************************************************
 *
 * Perform DMA to/from different PIF RAM address space (64 bytes)
 */

/* THIS SubTest has been removed, with real boot software,
the PIF does not allow one to randomly read and write the 
RAM locations without observing some protocols. 
*/
int
siTestDma(TEST_REF *test_ref)
{
    int         i, j, ret, size;
    unsigned int    addr, pifAddr, ramAddr;
    int         errorCount = 0;

    /*
     * Initialize RDRAM (64 bytes) with data = address
     */
    errlog(DEBUG, "--- SI DMA: initializing RDRAM address");
    addr = dgRdramFree;
    for (i = 0; i < 16; i++) {
        if (dgTestReg(addr, addr, addr)) {
                errorCount++;
        }
        addr += 4;
    }

    ramAddr = dgRdramFree;
    pifAddr = PIF_RAM_START;

    /* DMA: 64 bytes PIF_RAM <- RDRAM */
    errlog(DEBUG, "--- SI DMA: PIF_RAM (%08x) <- RDRAM (%08x)",
        pifAddr, ramAddr);
    siDmaCopy(DIR_WRITE, pifAddr, ramAddr); /* Start DMA */
    siPollStatus(SI_STATUS_DMA_BUSY, 1);    /* Wait for DMA busy to clear */
    if (siCompare(pifAddr, ramAddr, 64)) {  /* Compare data */
        errorCount++;
    }
    errlog(DEBUG, "--- SI DMA: checking for interrupt");
    siPollStatus(SI_STATUS_INTERRUPT, 0);   /* Wait for interrupt bit set */
    dgWriteWord(SI_STATUS_REG, 0);      /* Clear interrupt */
    siPollStatus(SI_STATUS_INTERRUPT, 1);   /* Interrupt bit should clear */

    /* DMA: 64 bytes PIF_RAM -> RDRAM */
    ramAddr = dgRdramFree+64;
    errlog(DEBUG, "--- SI DMA: PIF_RAM (%08x) -> RDRAM (%08x)",
        pifAddr, ramAddr);
    siDmaCopy(DIR_READ, pifAddr, ramAddr);  /* Start DMA */
    siPollStatus(SI_STATUS_DMA_BUSY, 1);    /* Wait for DMA busy to clear */
    if (siCompare(pifAddr, ramAddr, 64)) {  /* Compare data */
        errorCount++;
    }
    errlog(DEBUG, "--- SI DMA: checking for interrupt");
    siPollStatus(SI_STATUS_INTERRUPT, 0);   /* Wait for interrupt bit set */
    dgWriteWord(SI_STATUS_REG, 0);      /* Clear interrupt */
    siPollStatus(SI_STATUS_INTERRUPT, 1);   /* Interrupt bit should clear */

    return(errorCount);

}  /* siTestDma */


/**************************************************************************
 *
 * The following functions are derived from IOSIM environment
 *
 **************************************************************************/

/**************************************************************************
 * Poll SI status register for bit pattern to either be set or cleared
 */
static int
siPollStatus(unsigned int bits, int cleared)
{
    /* Poll SI status register for the statBits set */

    unsigned int stat;

    while (1) {
        if (dgReadWord(SI_STATUS_REG, &stat)) return (1);
        errlog (DEBUG,"SI Status Read is %08x",stat);
        if (cleared) {
            if (!(stat & bits)) break;
        }
        else {
            if (stat & bits) break;
        }
    }

    return((int)stat);

}  /* siPollStatus */


/**************************************************************************
 * Perform SI I/O write
 */
int
siIoWrite(unsigned int addr, unsigned int data)
{
    siPollStatus(SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY, 1);
    dgWriteWord(addr, data);
    return(0);

}  /* siIoWrite */


/**************************************************************************
 * Perform SI I/O read
 */
unsigned int
siIoRead(unsigned int addr)
{
    unsigned int data;

    siPollStatus(SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY, 1);
    dgReadWord(addr, &data);
    return(data);

}  /* siIoRead */


/**************************************************************************
 * Start SI DMA transaction between RDRAM and ROM
 */
int
siDmaCopy(int dir, unsigned int siAddr, unsigned int dramAddr)
{
    int ret;
    unsigned int stat;
    unsigned int buf;

    ret = 0;

    /* wait for dma not busy */
    siPollStatus(SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY, 1);

    if (dgWriteWord(SI_DRAM_ADDR_REG, dramAddr)) return (1);

    /* verify the address write */
    if (dgReadWord (SI_DRAM_ADDR_REG, &buf) ) return (1);
    if ( buf != dramAddr) {
        errlog (ERR_SEVERE,
        "SI Dram Addr Reg not written correctly actual = %08x, expected = %08x",
        buf, dramAddr);
    }

    switch (dir) {
        case DIR_READ: {            /* PIF_RAM -> RDRAM */
            if (dgWriteWord(SI_PIF_ADDR_RD64B_REG, siAddr)) return(1);
            break;
        }
        case DIR_WRITE: {           /* PIF_RAM <- RDRAM */
            if (dgWriteWord(SI_PIF_ADDR_WR64B_REG, siAddr)) return (1);
            break;
        }
        default: {
            ret = 1;
        }
    }  /* switch */

    return(ret);

}  /* siDmaCopy */


/**************************************************************************
 * Perform 32-bit compare between SI and RDRAM
 */
int
siCompare(unsigned int siAddr, unsigned int rdramAddr, int nbytes)
{
    /* Compare 'nbytes' bytes between source 'siAddr' and destination
     * 'rdramAddr'
     * 'nbytes' must be even and addresses word-aligned
     */

    int         i, errorCount;
    unsigned int    w1, w2;

    errorCount = 0;

    siAddr &= 0xFFFFFFFC;   /* Ensure addresses are word-aligned */
    rdramAddr &= 0xFFFFFFFC;

    i = 0;
    while (i < nbytes) {
        w1 = siIoRead(siAddr+i);
        dgReadWord(rdramAddr+i, &w2);
        i += 4;

        if (i > nbytes ) {
            /* Here, compare the LSB 2 bytes only */
            if ((w1 & 0xFFFF0000) != (w2 & 0xFFFF0000)) {
                errlog(ERR_SEVERE,
                   "data miscompare - si = (%08x:%08x), ram = (%08x:%08x)",
                   siAddr+(i-4), (w1 & 0xFFFF0000), rdramAddr+(i-4),
                   (w2 & 0xFFFF0000));
                errorCount++;
                break;
            }
        } else
            if (w1 != w2) {
                errlog(ERR_SEVERE,
                   "data miscompare - si = (%08x:%08x), ram = (%08x:%08x)",
                   siAddr+(i-4), w1, rdramAddr+(i-4), w2);
                errorCount++;
                break;
            }
    }  /* while */

    return(errorCount);

}  /* siCompare */




int
siReadRom(TEST_REF *test_ref)
{
    int         errorCount = 0;
    int i;
    unsigned int rbuf;

    for ( i = 0 ; i < 496; i++) {

    if (dgReadWord( PIF_ROM_START + (4*i) , &rbuf)) return (1);

    errlog(DEBUG,"Pif Contents @ %08x  is %08x",(PIF_ROM_START + (4*i)),rbuf);

    }
    return(errorCount);

}  /* siReadRom */

/* Data table */
static unsigned int resetDataTable[] = {


        0xff0100ff,
        0xffffffff,
        0xff0100ff,
        0xffffffff,
        0xff0100ff,
        0xffffffff,
        0xff0100ff,
        0xffffffff,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000
};
static unsigned int channelDataTable[] = {

        0xff010401,
        0xffffffff,
        0xff010401,
        0xffffffff,
        0xff010401,
        0xffffffff,
        0xff010401,
        0xffffffff,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000,
        0x00000000
};


unsigned char rdbuf[64];

static unsigned int resetDataTableSize= sizeof(resetDataTable)/sizeof(unsigned int);
static unsigned int channelDataTableSize= sizeof(channelDataTable)/sizeof(unsigned int);


/* This test performs no compares, but it goes through the action
* of resetting, then reading the external conroller, if it is plugged in.
* the fact that the test completes indicates the external joy bus
* does not hang the si interface 
*/
int
siReadController(TEST_REF *test_ref)
{
    int         errorCount = 0;
    int i;
    int PifRdPointer;
    unsigned int * prdbuf;
    unsigned int buf;


   /* Reset the channels with reset channel write dma  */
    errlog(DEBUG," Resetting channels");

    siPollStatus(SI_STATUS_DMA_BUSY | SI_STATUS_RD_BUSY, 1);
    /* write pif reset all channels bit */
    dgWriteWord(0x1fc007fc, 0x10);
    /* wait for write to complete */
    siPollStatus(SI_STATUS_RD_BUSY, 1);


    /* perform pif macro now to reset the channels */
    errlog (DEBUG,"Performing Pif Macro Command for resetting the channels");

    PifRdPointer = dgRdramFree + 0x00 ;

    /* kick off the dma pif to rdram */
#ifdef LOGIC_ANALYZER
    dgWait("Ready for pif macro read dma to reset channels trigger la ");
#endif
    siDmaCopy(DIR_READ, PIF_RAM_START, PifRdPointer);

    /* wait for dma to finish */
    siPollStatus(SI_STATUS_DMA_BUSY, 1);


/* Channel Descriptor */
    errlog(DEBUG," Writing the Channel descriptor");

    /* Stuff the channel descriptor  data table in rdram */
    if (dgWriteMem(dgRdramFree, 64, ((char *)channelDataTable))) return (1);

    /* verify rdram was loaded  correctly */
    if (dgReadMem (dgRdramFree, 64, rdbuf)) return (1);
    prdbuf = (unsigned int *) rdbuf;
    for (i = 0; i < 16 ; i++) {
        errlog(DEBUG,"Channel Descriptor Data for DMA @Rdram(%x) Data =  %08x",
        (dgRdramFree +(i*4)), *(prdbuf+i) );
        if ((*(prdbuf+i) != channelDataTable[i])) {
           errorCount ++;
           errlog(ERR_SEVERE,
           " Failed Rdram Memory Load index %x actual = %08x, expected = %08x",
                     i,*(prdbuf+i), channelDataTable[i] );
        }
    }

    /* dma to pif ram to describe the controller channels */


#ifdef LOGIC_ANALYZER
     dgWait("Ready for pif write dma trigger la "); */
#endif
    siDmaCopy(DIR_WRITE, PIF_RAM_START, dgRdramFree);



/* end of Channel Description load */



    /* trash rdram to insure the pif transfer to rdram overwrites it */
    for (i = 0; i < 16; i++) {
    dgWriteWord((dgRdramFree +(i*4)), 0xdeaddead);
    }

/* Perform the PIf Macro */
errlog (DEBUG,"Performing Pif Macro Command to Read controller data");

    /* DMA from PIF to RDRAM to get the controller data */
    PifRdPointer = dgRdramFree + 0x00 ;

    /* kick off the dma pif to rdram */
#ifdef LOGIC_ANALYZER
    dgWait("Ready for pif read dma trigger la ");
#endif
    siDmaCopy(DIR_READ, PIF_RAM_START, PifRdPointer);

    /* wait for dma to finish */
    siPollStatus(SI_STATUS_DMA_BUSY, 1);

    /* read and dump the pif read buffer from Rdram */
    if (dgReadMem (PifRdPointer, 64, rdbuf) ) return (1);
    for (i = 0; i < 16 ; i++) {
           errlog(DEBUG,
           " PIF Read data in Rdram address %08x , is %08x ",
      (PifRdPointer +(i*4)) ,*(prdbuf+i));
        }


    return(errorCount);

}  /* siReadController */