Ultra 64 Memory Map
	Release 30


	RCP memory map
	------------------------------------------------------------
	0x0000_0000 .. 0x007f_ffff	RDRAM memory
	0x0080_0000 .. 0x03ef_ffff	Rsvd
	0x03f0_0000 .. 0x03ff_ffff	RDRAM registers
	0x0400_0000 .. 0x04ff_ffff	RCP registers (see below)
	0x0500_0000 .. 0x05ff_ffff	cartridge domain 2
	0x0600_0000 .. 0x07ff_ffff	cartridge domain 1
	0x0800_0000 .. 0x0fff_ffff	cartridge domain 2
	0x1000_0000 .. 0x1fbf_ffff	cartridge domain 1
	0x1fc0_0000 .. 0x1fc0_07bf	PIF Boot Rom 
	0x1fc0_07c0 .. 0x1fc0_07ff	PIF RAM
	0x1fc0_07fc .. 0x1fc0_07ff	PIF STATUS Reg (in pif ram)
	0x1fc0_0800 .. 0x1fcf_ffff	Rsvd
	0x1fd0_0000 .. 0x7fff_ffff	cartridge domain 1
	0x8000_0000 .. 0xffff_ffff	external SysAD device


Power Up 
Settings RDRAM memory
-------	------------------------------------------------------------
X	0x0000_0000 .. 0x001f_ffff	RDRAM 0
X	0x0020_0000 .. 0x003f_ffff	RDRAM 1
X	0x0040_0000 .. 0x005f_ffff	RDRAM 2
X	0x0060_0000 .. 0x007f_ffff	RDRAM 3
			RDRAM memory may be organized as any combination
			of 1MB and 2MB RDRAM chips up to a total of 8MB



	SP memory
	------------------------------------------------------------
X	0x0400_0000 .. 0x0400_0fff	SP DMEM (read/write)
X	0x0400_1000 .. 0x0400_1fff	SP IMEM (read/write)


	SP CP0 registers
	------------------------------------------------------------
	0x0404_0000	SP dram DMA address (read/write)
0			[11:0]	DMEM/IMEM address
0			[12]	0 = DMEM; 1 = IMEM;

	0x0404_0004	SP mem DMA address (read/write)
0			[23:0]	RDRAM address

	0x0404_0008	SP read DMA length (read/write)
0			[11:0]	length
0			[19:12]	count
0			[31:20]	skip

	0x0404_000c	SP write DMA length (read/write)
0			[11:0]	length
0			[19:12]	count
0			[31:20]	skip

	0x0404_0010	SP status (write)
			[0]	clear halt
			[1]	set halt
			[2]	clear broke
			[3]	clear rsp interrupt
			[4]	set rsp interrupt
			[5]	clear single step
			[6]	set single step
			[7]	clear interrupt on break
			[8]	set interrupt on break
			[9]	clear signal 0
			[10]	set signal 0
			[11]	clear signal 1
			[12]	set signal 1
			[13]	clear signal 2
			[14]	set signal 2
			[15]	clear signal 3
			[16]	set signal 3
			[17]	clear signal 4
			[18]	set signal 4
			[19]	clear signal 5
			[20]	set signal 5
			[21]	clear signal 6
			[22]	set signal 6
			[23]	clear signal 7
			[24]	set signal 7

	0x0404_0010	SP status (read)
1			[0]	halt
0			[1]	broke
0			[2]	dma busy
0			[3]	dma full
0			[4]	io full
0			[5]	single step
0			[6]	interrupt on break
0			[7]	signal 0
0			[8]	signal 1
0			[9]	signal 2
0			[10]	signal 3
0			[11]	signal 4
0			[12]	signal 5
0			[13]	signal 6
0			[14]	signal 7

	0x0404_0014	SP DMA full (read)
0			[0]	dma full

	0x0404_0018	SP DMA busy (read)
0			[0]	dma busy

	0x0404_001c	SP semaphore (read)
0			[0]	semaphore flag (set on read)

	0x0404_001c	SP semaphore (write)
			[]	clear semaphore flag


	SP registers
	------------------------------------------------------------
	0x0408_0000	SP pc (read/write)
0			[11:0]	program_counter

	0x0408_0004	SP IMEM BIST status (write)
			[0]	bist check
			[1]	bist go
			[2]	clear bist


	0x0408_0004	SP IMEM BIST status (read)
0			[0]	bist check
0			[1]	bist go
0			[2]	bist done
0			[6:3]	bist fail


	DP command registers
	------------------------------------------------------------
	0x0410_0000	DP CMD DMA start (read/write)
X			[23:0] DMEM/RDRAM start address

	0x0410_0004	DP CMD DMA end (read/write)
X			[23:0] DMEM/RDRAM end address

	0x0410_0008	DP CMD DMA current (read)
0			[23:0] DMEM/RDRAM current address

	0x0410_000c	DP CMD DMA status (write)
			[0]	clear xbus_dmem_dma
			[1]	set xbus_dmem_dma
			[2]	clear freeze
			[3]	set freeze
			[4]	clear flush
			[5]	set flush
			[6]	clear tmem counter
			[7]	clear pipe counter
			[8]	clear cmd counter
			[9]	clear clock counter

	0x0410_000c	DP CMD DMA status (read)
0			[0]	xbus_dmem_dma
0			[1]	freeze
0			[2]	flush
1			[3]	start_gclk
0			[4]	tmem busy
1			[5]	pipe busy
0			[6]	cmd busy
1			[7]	cbuf ready
X			[8]	dma busy
0			[9]	end valid
0			[10]	start valid

	0x0410_0010	clock counter (read)
X			[23:0]	clock counter

	0x0410_0014	CMD buffer busy counter (read)
X			[23:0]	clock counter

	0x0410_0018	DP pipe busy counter (read)
X			[23:0]	clock counter

	0x0410_001c	TMEM load counter (read)
X			[23:0]	clock counter


	DP span registers
	------------------------------------------------------------
	0x0420_0000	DP TMEM BIST status (write)
			[0]	bist check
			[1]	bist go
			[2]	clear bist


	0x0420_0000	DP TMEM BIST status (read)
0			[0]	bist check
0			[1]	bist go
X			[2]	bist done
X			[10:3]	bist fail

	0x0420_0004	DP Span Test Mode
0			[0]	Span Buffer Test Access Enable

	0x0420_0008	DP Span Buffer Test Address Register
X			[1:0] 	Data Field Select
X			[2]	Span Buffer Device Select
X			[6:3]	Span Buffer Address

	0x0420_000c	DP Span Buffer Test Data Register
X			[31:0]	Span Buffer Data

	MI registers
	------------------------------------------------------------
	0x0430_0000	mode (write)
			[6:0]	init length
			[7]	clear init mode
			[8]	set init mode
			[9]	clear ebus test mode
			[10]	set ebus test mode
			[11]	clear dp interrupt
			[12]	clear RDRAM register mode
			[13]	set RDRAM register mode

	0x0430_0000	mode (read)
0			[6:0]	init length
0			[7]	init mode
0			[8]	ebus test mode
0			[9]	RDRAM register mode

	0x0430_0004	version (read)
2			[7:0]	io version  V1.0 = 1
2			[15:8]	rac version V1.0 = 1
1			[23:16]	rdp version V1.0 = 1
2			[31:24]	rsp version V1.0 = 1

	0x0430_0008	interrupt (read)
0			[0]	sp interrupt
0			[1]	si interrupt
0			[2]	ai interrupt
0			[3]	vi interrupt
0			[4]	pi interrupt
0			[5]	dp interrupt

	0x0430_000c	mask (write)
			[0]	clear sp interrupt mask
			[1]	set sp interrupt mask
			[2]	clear si interrupt mask
			[3]	set si interrupt mask
			[4]	clear ai interrupt mask
			[5]	set ai interrupt mask
			[6]	clear vi interrupt mask
			[7]	set vi interrupt mask
			[8]	clear pi interrupt mask
			[9]	set pi interrupt mask
			[10]	clear dp interrupt mask
			[11]	set dp interrupt mask

	0x0430_000c	mask (read)
0			[0]	sp interrupt mask
0			[1]	si interrupt mask
0			[2]	ai interrupt mask
0			[3]	vi interrupt mask
0			[4]	pi interrupt mask
0			[5]	dp interrupt mask


	VI register
	------------------------------------------------------------
	0x0440_0000	status (read/write)
0			[9:0]	TBD

	0x0440_0004	origin (read/write)
0			[23:0]	start RDRAM address

	0x0440_0008	width (read/write)
0			[11:0]	horizontal line width

	0x0440_000c	v int (read/write)
0x3ff			[9:0]	vertical line interrupt

	0x0440_0010	v current (write)
			[]      clears interrupt

	0x0440_0010	v current (read)
0			[9:0]	current vertical line

	0x0440_0014	video timing (read/write)
1			[7:0]	horizontal sync width
0			[15:8]	burst width
0			[19:16]	vertical sync width
0			[29:20] burst start

	0x0440_0018	v sync (read/write)
0			[9:0]	vertical sync width

	0x0440_001c	h sync (read/write)
2047			[11:0]	horizontal sync width
0			[20:16]	leap pattern

	0x0440_0020	h sync leap (read/write)
0			[9:0]	horizontal sync leap B
0			[25:16]	horizontal sync leap A

	0x0440_0024	h video (read/write)
0			[9:0]	horizontal video end
0			[25:16]	horizontal video start

	0x0440_0028	v video (read/write)
0			[9:0]	vertical video end
0			[25:16]	vertical video start

	0x0440_002c	v burst (read/write)
0			[9:0]	vertical burst end
0			[25:16]	vertical burst start

	0x0440_0030	x scale (read/write)
0			[11:0]	x scale
0			[27:16]	x offset

	0x0440_0034	y scale (read/write)
0			[11:0]	y scale
0			[27:16]	y offset

	0x0440_0038	test data (read/write)
X			[31:0]	test data

	0x0440_003c	test address (read/write)
0			[31:0]	test address


	AI registers
	------------------------------------------------------------
	0x0450_0000	dram address (write)
			[23:0]	starting RDRAM address

	0x0450_0004	length (read/write)
0			V1.0: [14:0]	transfer length
0			V2.0: [17:0]

	0x0450_0008	enable (write)
			[0]	dma enable

	0x0450_000c	status (write)
			[]	clear interrupt

	0x0450_000c	status (read)
0			[31]	full
0			[30]	busy

	0x0450_0010	audio dac period (write)
			[13:0]	vclk_divider_minus_1

	0x0450_0014	audio dac bit clock half period (write)
			[3:0]	vclk_divider_minus_1


	PI registers
	------------------------------------------------------------
	0x0460_0000	dram address (read/write)
X			[23:0]	starting RDRAM address

	0x0460_0004	pbus address (read/write)
X			[31:0]	starting AD16 address

	0x0460_0008	read length (read/write)
X			[23:0]	DMA read data length

	0x0460_000c	write length (read/write)
X			[23:0]	DMA write data length

	0x0460_0010	status (write)
			[1]	clear interrupt
			[0]	reset PI controller (and abort current operation)
						    (and clear interrupt)

	0x0460_0010	status (read)
0			[2]	error
0			[1]	IO operation in progress.
0			[0]	data transfer in progress.

	0x0460_0014	dom1 lat (read/write)
0xff			[7:0]	region 1 device latency

	0x0460_0018	dom1 pwd (read/write)
0xff			[7:0]	region 1 device read/write strobe pulse width

	0x0460_001c	dom1 pgs (read/write)
0			[3:0]	region 1 device page size

	0x0460_0020	dom1 rls (read/write)
0x3			[1:0]	region 1 read/write release

	0x0460_0024	dom2 lat (read/write)
0xff			[7:0]	region 2 ROM device latency

	0x0460_0028	dom2 pwd (read/write)
0xff			[7:0]	regopm 2 device read/write strobe pulse width

	0x0460_002c	dom2 pgs (read/write)
0			[3:0]	region 2 page size

	0x0460_0030	dom2 rls (read/write)
0x3			[1:0]	retion 2 read/write release

	0x0460_0034	reserved
	0x0460_0038	reserved


	RI registers
	------------------------------------------------------------
	0x0470_0000	mode (read/write)
 			[1:0]	operating mode
1			[2]	stop_t_active
1			[3]	stop_r_active

	0x0470_0004	config (read/write)
0			[5:0]	current control input
0			[6]	current control enable

	0x0470_0008	current load (write)
			[]	any write updates current control register

	0x0470_000c	select (read/write)
0			[3:0]	receive select
0			[3:0]	transmit select

	0x0470_0010	refresh (read/write)
X			[7:0]	clean refresh delay
X			[15:8]	dirty refresh delay
0			[16]	refresh bank
0			[17]	refresh enable
0			[18]	refresh optimize
0			[22:19] refresh multibank device

	0x0470_0014	latency (read/write)
-1			[3:0]   DMA latency/overlap

	0x0470_0018	error (read)
0			[0]	nack error
0			[1]	ack error
0			[2]	overrange

	0x0470_0018	error (write)
			[]	write clears all error bits

	0x0470_001c	bank status (read)
0			[7:0]	bank[7:0] valid bits
0xff			[15:8]	bank[7:0] dirty bits

	0x0470_001c	bank status (write)
			[]	write clears valid and sets dirty bits


	SI registers
	------------------------------------------------------------
	0x0480_0000	dram address (read/write)
X			[23:0]	RDRAM address for DMA

	0x0480_0004	ad rd 64 (write)
			[]	PIF address for DMA 
				a write causes a 64 byte DMA write

	0x0480_0008	reserved

	0x0480_0010	ad wr 64 (write)
			[]	PIF address for DMA
				a write causes a 64 byte DMA read

	0x0480_0014	reserved

	0x0480_0018	status (write)
			[]	clear interrupt

	0x0480_0018	status (read)
X			[0]	dma busy
X			[1]  	io busy
0			[3]	dma error
0			[12]	interrupt


	Release Notes
	------------------------------------------------------------
	 1 - Initial release.
	 2 - Updated SP CP0 registers and DP command registers.
	 3 - Added RDRAM memory ranges.
	 4 - Added BIST registers.
	 5 - Fixed SP BIST address.
	 6 - Fixed SP and DP BIST bit definitions.
	 7 - Updated RI register definitions.
	 8 - Updated SI register definitons.
	 9 - Added DP frozen and RI latency registers.
	10 - Added SP signal, DP interrupt registers.
	11 - Added cbuf ready.
	12 - Added DP Span Buffer Test Registers.
	13 - Updated AI registers.
	14 - Added dma busy to DP registers.
	15 - Added semaphore to SP registers.
	16 - Added interrupt on break flag.
	17 - Added refresh optimize to RI refresh register.
	18 - Added RDRAM register mode to MI mode register.
	19 - Fixed external device address range and MI mode register.
	20 - Added video interrupt clear definition.
	21 - Updated register defs in VI and PI.
	22 - Updated CMD status register.
	23 - Broke PIF address range into 3 separate areas, rsvd for left over.
	24 - AI Length is 15 bits for RCP1.0 18 bits for RCP2.0.
	25 - Numerous typo fixes.
	26 - Clarified PIF address ranges per Nintendo request.
	27 - Added RI refresh and reset control registers.
	28 - Fixed typo in RI dirty/valid bit description.
	29 - Clarified RDRAM address range as 8MB, rsvd for remainder
	30 - Added power up settings of all bits on the rcp