RI/RAC/RDRAM initialization sequence:

 0) Following RAC reset, the RAC inputs are:
	SynClkIn	- SynClkFd
	TData		- 0x0 (unknown during reset)
	B*Sel		- 0x0
	R*Sel		- 0x0
	Reset		- 0x0
	StopT		- 0x1 (low during reset)
	StopR		- 0x1 (low during reset)
	PwrUp		- 0x1
	ExtBE		- 0x0
	PhStall		- 0x0
	CCtlLd		- 0x0
	CCtlEn		- 0x0
	CCtlI		- unknown
	SCANMode	- 0x0
	SCANClk		- 0x0
	SCANEn		- 0x0
	SCANIn		- 0x0
	BISTMode	- 0x0
	IOSTMode	- 0x0
	ByPass		- 0x0
	ByPSel		- 0x1
	tclkASIC	- 0x0
	rclkASIC	- 0x0
	
 1) Enable RAC auto-calibration current control.
	set CCtlI to 0x00
	set CCtlEn to 1

	write 0x0000_0040 @ 0x0470_0004

 2) Wait for new current control value.

	delay 4096 RCP clock cycles

 3) Load the current control register.
	set CCtlLd to 1 for one RCP clock

	write 0x0000_0000 @ 0x0470_0008

 4) Set transmit and receive selects.
	set R*Sel to 4
	set B*Sel to 1

	write 0x0000_0014 @ 0x0470_000c

 5) Reset all RDRAM devices.
	set BusEnable to 0xff
	set StopT to 0x0
	set StopR to 0x0

	write 0x0000_0000 @ 0x0470_0000

 6) Wait for RDRAM devices to reset

	delay 100 RCP clock cycles

 7) Enable RDRAM access
	set default BusEnable to 0x00 (auto-enable)
	set default StopT to 0x1 (auto-enable)
	set default StopR to 0x1 (auto-enable)

	write 0x0000_000e @ 0x0470_0000

 8) Initialize the Delay register in all RDRAMs.
	set AckWinDelay to 0x28
	set ReadDelay to 0x38
	set AckDelay to 0x18
	set WriteDelay to 0x08

	write 0x0000_010f @ 0x0430_0000
	write 0x1808_2838 @ 0x03f8_0008

10) Initialize the RefRow register in all RDRAMs.
	global set RowField to 0x0
	global set BankField to 0x0

	write 0x0000_0000 @ 0x03f8_0014

11) Move all RDRAMs to the top of the address space.
	global set IdField to 0x0004

	write 0x8000_0000 @ 0x03f8_0004

12) Place all RDRAMs at 2 Mbyte boundaries and determine the size of
    each RDRAM.

	next_device = 0
	next_id = 0
	next_reg = 0x03f0_0000
	next_1_id = 0
	next_1_reg = 0x03f0_0000
	next_1_mem = 0
	next_2_id = 0
	next_2_reg = 0x03f0_0000
	next_2_mem = 0
	multibank = 0

	loop
		/* move the next RDRAM to the next 2 MByte slot */
		write next_id @ 0x03f0_8004

		/* enable the RDRAM */
		write 0xc680_0000 @ (next_reg + 0xc)

		/* determine the RDRAM size */
		write 0x0000_2000 @ 0x0430_0000
		read device_type[next_device] @ (next_reg + 0x0)
		write 0x0000_1000 @ 0x0430_0000

		case device_type[next_device]
		   0    : exit loop

		   1 MB :

		   2 MB : next_1_id = next_1_id + 0x0800_0000
		          next_1_reg = next_1_reg + 0x0000_0800
		          next_1_mem = next_1_mem + 0x0020_0000
			  multibank = (multibank << 1) + 1

		/* determine the RDRAM manufacture */
		write 0x0000_2000 @ 0x0430_0000
		read device_manufacture @ (next_reg + 0x24)
		write 0x0000_1000 @ 0x0430_0000

		/* write the RasInterval register based on the manufacture */
		if device_manufacture == NEC then
		   write 0x101c_0a04 @ (next_reg + 0x18)
		else
		   write 0x????_???? @ (next_reg + 0x18)

		next_device = next_device + 1
		next_id = next_id + 0x8
		next_reg = next_reg + 0x800

13) Swap so that all the 2Mbyte RDRAMs preceed the 1 Mbyte RDRAMs.

	/* Reinitialize all the RDRAMs */
	write 0xc480_0000 @ 0x03f8_000c
	write 0x8000_0000 @ 0x03f8_0004

	/* Group the RDRAMs in 1 Mbyte and 2 Mbyte blocks */
	for (i = 0 to next_device-1)
	   case device_type[i]
	      1 MB : /* Move the RDRAM to the next 1 Mbyte slot */
	             write next_1_id @ 0x03f0_8004
	             write 0xc680_0000 @ (next_1_reg + 0xc)

	             /* Tickle the RDRAM */
	             read dont_care @ next_1_mem + 0x0_0000
	             read dont_care @ next_1_mem + 0x8_0000
	             read dont_care @ next_1_mem + 0x0_0000
	             read dont_care @ next_1_mem + 0x8_0000

	             next_1_id = next_1_id + 0x0400_0000
	             next_1_reg = next_1_reg + 0x0000_0400
	             next_1_reg = next_1_mem + 0x0010_00000

	      2 MB : /* Move the RDRAM to the next 2 Mbyte slot */
	             write next_2_id @ 0x03f0_8004
	             write 0xc680_0000 @ (next_2_reg + 0xc)

	             /* Tickle the RDRAM */
	             read dont_care @ next_2_mem + 0x00_0000
	             read dont_care @ next_2_mem + 0x08_0000
	             read dont_care @ next_2_mem + 0x10_0000
	             read dont_care @ next_2_mem + 0x18_0000
	             read dont_care @ next_2_mem + 0x00_0000
	             read dont_care @ next_2_mem + 0x08_0000
	             read dont_care @ next_2_mem + 0x10_0000
	             read dont_care @ next_2_mem + 0x18_0000

	             next_2_id = next_2_id + 0x0800_0000
	             next_2_reg = next_2_reg + 0x0000_0800
	             next_2_reg = next_2_mem + 0x0020_00000

21) Set refresh interval and enable refresh
	set the dirty refresh interval to 0x36
	set the clean refresh interval to 0x36
	clear the refresh row count
	enable refresh optimize
	enable refresh
	set the number of 2 Mbyte devices

	write (0x63634 | (multibank << 19)) @ 0x0470_0010


Notes:

1) This procedure assumes that the first 2 Mbyte RDRAM in the Rambus
   serial init chain is a 9 bit memory and that video will always be
   located in the first 2 Mbytes of memory. All 1 Mbyte RDRAMs and
   any other 2 Mbytes RDRAMs may be either 8 bit or 9 bit memories.