============================================================================
RI/RDRAM register read/write operations
============================================================================

To read/write an RI register, use the address described in the
"RI Registers" section below.

To write an RDRAM register, use the following format:

	Addresses between 0x03f?_???? are decoded as follows:
	[31:20] - 0x03f
		  Select RDRAM registers

	[19]    - Enable global write.
		  0 - Write one RDRAM.
		  1 - Write all RDRAMs.

	[18:10]	- RDRAM packets address bits [29:21].

	[9:0]	- RDRAM packet address bits [9:0].

	All other RDRAM packet address bits ([35:30] and [20:10]) are set to
	0 for register writes.  Therefore, to write to RDRAM 0, use the
	addresses 0x03f0_0000 .. 0x03f0_03fc.  To write to RDRAM 1, use the
	addresses 0x03f0_0400 .. 0x03f0_07fc.  To write to both RDRAMs, use
	the addresses 0x03f8_0000 .. 0x03f8_03fc.  Note that these
	addresses will change for RCP 2.

To read an RDRAM register, use the following format:

	Addresses between 0x03f?_???? are decoded as follows:
	[31:20] - 0x03f
		  Select RDRAM registers

	[19]    - set to zero.

	[18:10]	- RDRAM packets address bits [29:21].

	[9:0]	- RDRAM packet address bits [9:0].

	All other RDRAM packet address bits ([35:30] and [20:10]) are set to
	0 for register reads.  Therefore, to read to RDRAM 0, use the
	addresses 0x03f0_0000 .. 0x03f0_03fc.  To read to RDRAM 1, use the
	addresses 0x03f0_0400 .. 0x03f0_07fc.  Also, because reading RDRAM
	registers is not consistent with reading RDRAM memory, you must also
	enable the CPU interface to format the RDRAM data.  Prior to reading
	an RDRAM register, issue the write:

		write 0x0000_2000 @ 0x0430_0000

	After reading the RDRAM registers, clear this mode by issuing the
	write:

		write 0x0000_1000 @ 0x0430_0000

Note that this entire initialization procedure will change for RCP 2 to
support 8 Mbit RDRAMs.


============================================================================
RI Registers
============================================================================

0x0470_0000	mode (read/write)
----------------------------------------------------------------------------
		[1:0]	operating mode
			This controls what smode packets are sent to the
			RDRAM over the BusEnable pin.  The options are:
			00 : Reset - force continuous smode packets.  If
			     this is asserted for 272 BusClk cycles, all
			     RDRAMs will reset.
			01 : Active - Send an smode packet every 4 BusClk
			     cycles.  The forces the RDRAMs to be
			     continuously active.  This mode is for debug
			     only.
			10 : Standby - Send an smode packet before each
			     RDRAM transaction.  This allows the RDRAMS to
			     enter standby mode following each transaction
			     and the reactivated at the start of each
			     transaction. This is the normal operating mode.
			11 : Reserved.

		[2]	stop_t_active
			This enables automatic powerdown of the RAC transmit
			logic while idle.
			0 : Disable transmit powerdown.  For debug only.
			1 : Enable transmit powerdown. Normal operating
			    mode.

		[3]	stop_r_active
			This enables automatic powerdown of the RAC receive
			logic while idle.
			0 : Disable receive powerdown.  For debug only.
			1 : Enable receive powerdown. Normal operating mode.


0x0470_0004	config (read/write)
----------------------------------------------------------------------------
		[5:0]	current control input
			This register drives the CCtlI input of the RAC.
			It supplies the Rambus current drive value in manual
			current control mode.

		[6]	current control enable
			This register drives the CCtlEn input of the RAC.
			It selects the automatic or manual current control.
			0 : Manual CCtl - current control value loaded from
			    current control input.
			1 : Automatic CCtl - current control value loaded
			    from automatic current control logic.


0x0470_0008	current load (write)
----------------------------------------------------------------------------
		[]	Any write causes a pulse on CCtlLd input of the RAC.
			This causes a new current control value to be
			loaded.


0x0470_000c	select (read/write)
----------------------------------------------------------------------------
		[3:0]	receive select
			This drives the RDsel and RCSel inputs of the RAC.
			See the RAC manual for a description.
			The only legal values for this register are:
			000 : Disable receive.
			100 : Enable receive.

		[3:0]	transmit select
			This drives the BDsel, BCSel and BESel inputs of the
			RAC.  See the RAC manual for a description.
			The only legal values for this register are:
			000 : Disable transmit.
			001 : Enable transmit.


0x0470_0010	refresh (read/write)
----------------------------------------------------------------------------
		[7:0]	clean refresh delay
			The delay following a clean refresh request.  The
			actual delay is this value + 2.

		[15:8]	dirty refresh delay
			The delay following a dirty refresh request.  The
			actual delay is this value + 2.

		[16]	refresh bank
			The next bank to be refreshed.  This register is
			incremented (inverted) following each refresh.

		[17]	refresh enable
			Enable automatic refresh.  The options are:
			0 - Disable automatic refresh.
			1 - Generate a refresh once each video horizontal
			    retrace.

		[18]	refresh optimize
			Enable refresh timing optimization.  This includes
			selecting clean refresh if the banks to be refreshed
			have not been written and clearing dirty banks.
			Options include:
			0 - Disable refresh optimize.
			1 - Enable refresh optimize.

		[19]	refresh multibank 0/1
			Indicated whether banks 0 and 1 are part of a
			a multibank (16 Mbit) device.  This only effects
			refresh optimization.  This register is only
			available in RCP 2.  Options include:
			0 - Banks 0 and 1 are in separate 8 Mbit devices.
			1 - Banks 0 and 1 are in the same 16 Mbit device.
			
		[20]	refresh multibank 2/3
			Indicated whether banks 2 and 3 are part of a
			a multibank (16 Mbit) device.  This only effects
			refresh optimization.  This register is only
			available in RCP 2.  Options include:
			0 - Banks 0 and 1 are in separate 8 Mbit devices.
			1 - Banks 0 and 1 are in the same 16 Mbit device.

		[21]	refresh multibank 4/5
			Indicated whether banks 4 and 5 are part of a
			a multibank (16 Mbit) device.  This only effects
			refresh optimization.  This register is only available
			in RCP 2.  Options include:
			0 - Banks 0 and 1 are in separate 8 Mbit devices.
			1 - Banks 0 and 1 are in the same 16 Mbit device.

		[22]	refresh multibank 6/7
			Indicated whether banks 6 and 7 are part of a
			a multibank (16 Mbit) device.  This only effects
			refresh optimization.  This register is only
			available in RCP 2.  Options include:
			0 - Banks 0 and 1 are in separate 8 Mbit devices.
			1 - Banks 0 and 1 are in the same 16 Mbit device.


0x0470_0014	latency (read/write)
----------------------------------------------------------------------------
		[3:0]   DMA latency/overlap
			Sets maximum DMA latency.  This is to allow the
			higher bandwidth video modes to operate.  The
			optimal (and default) value is 0xf and should not
			be changed unless required by the video mode.

0x0470_0018	error (read)
----------------------------------------------------------------------------
		[0]     nack error
			This bits is set if the RDRAM did not respond with
			a nack.  Only RDRAM memory R/W operations are
			checked. RDRAM register R/W operations will not
			effect this register.

		[1]     ack error
			This bits is set if the RDRAM did not respond with
			a ack.  Only RDRAM memory R/W operations are
			checked. RDRAM register R/W operations will not
			effect this register.

		[2]	overrange
			This bit is set if a memory access beyond the RDRAM
			memory limit (4 Mbyte for RCP 1, 8 Mbyte for RCP 2)
			is requested.


0x0470_0018	error (write)
----------------------------------------------------------------------------
		[]      any write clears all error bits


0x0470_001c	bank status (read/write)
----------------------------------------------------------------------------
		[7:0]	bank[7:0] dirty bits
			Status of the shadow RDRAM dirty bits.
			This register is only available in RCP 2.

		[7:0]	bank[7:0] valid bits
			Status of the shadow RDRAM valid bits.
			This register is only available in RCP 2.




============================================================================
RI/RAC/RDRAM initialization sequence:
============================================================================

 0) Following RAC reset, the RAC inputs are:
	SynClkIn	- SynClkFd
	TData		- 0x0 (unknown during reset)
	B*Sel		- 0x0
	R*Sel		- 0x0
	Reset		- 0x0
	StopT		- 0x1 (low during reset)
	StopR		- 0x1
	PwrUp		- 0x1
	ExtBE		- 0x0
	PhStall		- 0x0
	CCtlLd		- 0x0
	CCtlEn		- 0x0
	CCtlI		- unknown
	SCANMode	- 0x0
	SCANClk		- 0x0
	SCANEn		- 0x0
	SCANIn		- 0x0
	BISTMode	- 0x0
	IOSTMode	- 0x0
	ByPass		- 0x0
	ByPSel		- 0x1
	tclkASIC	- 0x0
	rclkASIC	- 0x0
	
 1) Enable RAC auto-calibration current control. (See below)
	set CCtlI to 0x00
	set CCtlEn to 1

	write 0x0000_0040 @ 0x0470_0004

    However, because the Auto current control in the RAC of RCP 1 is broken,
    we must instead disable auto-calibration current control. Instead of
    the above do the following:
	set CCtlI to 0x10
	set CCtlEn to 0

	write 0x0000_0010 @ 0x0470_0004

 2) Wait for new current control value.

	delay 4096 RCP clock cycles

 3) Load the current control register.
	set CCtlLd to 1 for one RCP clock

	write 0x0000_0000 @ 0x0470_0008

 4) Set transmit and receive selects
	set R*Sel to 4
	set B*Sel to 1

	write 0x0000_0014 @ 0x0470_000c

 5) Reset all RDRAM devices.
	set BusEnable to 0xff
	set StopT to 0x0
	set StopR to 0x0

	write 0x0000_0000 @ 0x0470_0000

 6) Wait for RDRAM devices to reset

	delay 100 RCP clock cycles

 7) Enable RDRAM access
	set default BusEnable to 0x00 (auto-enable)
	set default StopT to 0x1 (auto-enable)
	set default StopR to 0x1 (auto-enable)

	write 0x0000_000e @ 0x0470_0000

 8) Initialize the Delay register in all RDRAMs.
	set AckWinDelay to 0x28
	set ReadDelay to 0x38
	set AckDelay to 0x18
	set WriteDelay to 0x08

	write 0x0000_010f @ 0x0430_0000
	write 0x1808_2838 @ 0x03f8_0008

 9) Enable RDRAM auto-calibration current control in all RDRAMs.  This
    is optional and my not be implemented.
	global set CE to 0x1, clear all other Mode register bits.

	write 0x8000_0000 @ 0x03f8_000c

10) Initialize the RefRow register in all RDRAMs.
	global set RowField to 0x0
	global set BankField to 0x0

	write 0x0000_0000 @ 0x03f8_0014

11) Move all RDRAMs to the top of the address space
	global set IdField to 0x0001

	write 0x0800_0000 @ 0x03f8_0004

12) Move the first RDRAM to the bottom of the address space.
	set IdField of first RDRAM to 0x0000

	write 0x0000_0000 @ 0x03f0_0404

13) Activate the first RDRAM.
	set CE and DE of the first RDRAM

	write 0x8200_0000 @ 0x03f0_000c

14) Activate the second RDRAM (no effect if second RDRAM is absent.)
	IdField already set to 0x0001
	set CE and DE of the second RDRAM

	write 0x8200_0000 @ 0x03f0_040c

15) Determine the first RDRAM type by reading the DeviceManufacture
    register.

	write 0x0000_2000 @ 0x0430_0000
	read 0x03f0_0024
	write 0x0000_1000 @ 0x0430_0000

16) Use the DeviceManufacture value to select a RasInterval value.
	set the RasInterval register of the first RDRAM

	write 0x101c_0a04 @ 0x03f0_0018 (for Manufacture == NEC)
	-or-
	write 0x????_???? @ 0x03f0_0018 (for Manufacture == non-zero)
	-or-
	not present (for Manufacture == zero) (illegal condition)

17) Determine the second RDRAM type by reading the DeviceManufacture
    register.

	write 0x0000_2000 @ 0x0430_0000
	read 0x03f0_0424
	write 0x0000_1000 @ 0x0430_0000

18) Use the DeviceManufacture value to select a RasInterval value.
	set the RasInterval register of the second RDRAM

	write 0x101c_0a04 @ 0x03f0_0418 (for Manufacture == NEC)
	-or-
	write 0x????_???? @ 0x03f0_0418 (for Manufacture == non-zero)
	-or-
	not present (for Manufacture == zero)

19) Tickle the first RDRAM

	read 0x0000_0000
	read 0x0008_0000
	read 0x0010_0000
	read 0x0018_0000
	read 0x0000_0000
	read 0x0008_0000
	read 0x0010_0000
	read 0x0018_0000

20) Tickle the second RDRAM (if present)

	read 0x0020_0000
	read 0x0028_0000
	read 0x0030_0000
	read 0x0038_0000
	read 0x0020_0000
	read 0x0028_0000
	read 0x0030_0000
	read 0x0038_0000

21) Set refresh interval and enable refresh
	set the dirty refresh interval to 0x38
	set the clean refresh interval to 0x36
	enable refresh
	enable refresh optimization

	write 0x0006_3634 @ 0x0470_0010