cc.ss
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module = cc
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* read the verilog sources */
read -f verilog ../src/cc_abs16n.v
read -f verilog ../src/cc_add12.v
read -f verilog ../src/cc_edge_add.v
read -f verilog ../src/cc_edge_booth.v
read -f verilog ../src/cc_edge_booth0.v
read -f verilog ../src/cc_edge_booth1.v
read -f verilog ../src/cc_edge_booth2.v
read -f verilog ../src/cc_edge_csa.v
read -f verilog ../src/cc_edge_ctrl.v
read -f verilog ../src/cc_edge_div.v
read -f verilog ../src/cc_inc4.v
read -f verilog ../src/cc_key.v
read -f verilog ../src/cc_key_gt.v
read -f verilog ../src/cc_key_mux.v
read -f verilog ../src/cc_key_clamp.v
read -f verilog ../src/cc_lerp.v
read -f verilog ../src/cc_lerp_booth.v
read -f verilog ../src/cc_lerp_booth0.v
read -f verilog ../src/cc_lerp_booth7.v
read -f verilog ../src/cc_lerp_booth8.v
read -f verilog ../src/cc_lerp_csa.v
read -f verilog ../src/cc_lerp_csa_add12.v
read -f verilog ../src/cc_lerp_csa_fa10.v
read -f verilog ../src/cc_lerp_csa_fa11.v
read -f verilog ../src/cc_lerp_csa_fa14.v
read -f verilog ../src/cc_lerp_csa_fa8.v
read -f verilog ../src/cc_lerp_csa_fa9.v
read -f verilog ../src/cc_lerp_csa_faso.v
read -f verilog ../src/cc_lerp_csa_ha1.v
read -f verilog ../src/cc_lerp_csa_ha3.v
read -f verilog ../src/cc_lerp_csa_ha5.v
read -f verilog ../src/cc_mxaa.v
read -f verilog ../src/cc_mxar.v
read -f verilog ../src/cc_mxca.v
read -f verilog ../src/cc_mxcr.v
read -f verilog ../src/cc_mxxa.v
read -f verilog ../src/cc_mxxr.v
read -f verilog ../src/cc_mxya.v
read -f verilog ../src/cc_mxyr.v
read -f verilog ../src/cc.v
current_design = cc
link
check_design > cc.lint
/* compile restrictions */
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* }
sub_modules = { cc_mxxr, cc_mxxa, cc_mxyr, cc_mxya, \
cc_mxar, cc_mxaa, cc_mxcr, cc_mxca, \
cc_lerp_booth, \
cc_abs16n, cc_add12, cc_inc4, \
cc_edge_ctrl, cc_edge_add, \
cc_key_clamp, cc_key_gt, cc_key_mux, \
cc_edge_booth, cc_edge_csa, cc_edge_div, \
cc_key}
foreach(module, sub_modules){
set_dont_touch module
}
set_dont_touch cc_lerp_csa_add12
set_dont_touch cc_lerp_csa_fa10
set_dont_touch cc_lerp_csa_fa11
set_dont_touch cc_lerp_csa_fa14
set_dont_touch cc_lerp_csa_fa8
set_dont_touch cc_lerp_csa_fa9
set_dont_touch cc_lerp_csa_faso
set_dont_touch cc_lerp_csa_ha1
set_dont_touch cc_lerp_csa_ha3
set_dont_touch cc_lerp_csa_ha5
current_design = cc_lerp_csa
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
set_max_transition 1.1 current_design
set_load 0.08 all_outputs()
compile -map_effort low -incremental_mapping
current_design = cc_lerp
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
set_max_transition 1.1 current_design
set_load 0.08 all_outputs()
compile -map_effort low -incremental_mapping -ungroup_all
set_dont_touch current_design
current_design = cc
/* setup operating conditions */
set_operating_conditions NOM
set_wire_load 128000 -mode top
/* timing/area constraints */
max_area 10000
set_input_delay 2.0 all_inputs()
set_driving_cell -cell dfntnb all_inputs()
create_clock gclk -period 14.0 -waveform {0 7.0}
set_driving_cell -none {gclk}
set_dont_touch_network {gclk}
set_drive 0 {gclk}
set_arrival 0 {gclk}
set_output_delay 4.0 -clock gclk all_outputs()
set_load 0.08 all_outputs()
set_max_transition 1.1 current_design
/* compile */
compile -map_effort high -ungroup_all
/* enforce naming restrictions for Compass tools */
change_names -rules compass_rules -hierarchy
/* standard reports & netlist */
module = cc
include "report.dc"
write -f edif -o cc.edf -hier cc
quit