reality_mon.v
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// $Id: reality_mon.v,v 1.1.1.1 2002/05/17 06:15:00 blythe Exp $
module reality_mon(clock, reset_l);
`include "rcp.vh"
`include "define.vh"
input clock;
input reset_l;
reg [1:256*8] vifilename;
reg [31:0] timelimit;
reg [31:0] cyclelimit;
reg [31:0] startdump;
reg [31:0] cycle_count;
reg [1:256*8] rambus_fn;
integer count;
integer tab_file_ptr; // output file pointer
initial begin
if ($test$plusargs("help")) begin
$display("general arguments include:");
$display(" +help - log this message");
$display(" +dump - generate a verilog dump file");
$display(" +adac_mon - log audio dac activity");
$display(" +cbuf_mon - log cbuf activity");
$display(" +cbus_mon - log cbus activity");
$display(" +mbus_mon - log mbus activity");
$display(" +xbus_mon - log xbus activity");
$display(" +cart_mon - log cartridge activity");
$display(" +mem_mon - log mem activity");
$display(" +span_mon - log span activity");
$display(" +spandata_mon - log span data read/write activity");
$display(" +r4200_mon - log 4200 activity");
$display(" +load_rom - load cartridge ROM from rom_?.data");
$display(" +load_rdram - load Rambus DRAM from rdram_reorderd_?.data");
$display(" +load_dmem - load SP DMEM from dmem_even.data & dmem_odd.data");
$display(" +load_imem - load SP IMEM from imem.data");
$display(" +load_pif - load PIF ROM from pif.data");
$display(" +cyclelimit=<cyc> - limit simulation to no more than <cyc> cycles");
$display(" +startdump=<cyc> - turn dump on at cycle <cyc>");
$display(" +enable_nmi - enable nmi generation from PIF");
$display(" +vitab=file - turn on dumping of video data for software monitor");
$display(" +mmap_rdram=file - load Rambus DRAM from memory mapped file.main and file.hidden");
$display("");
#1 $finish;
end
`ifdef GATE_LEVEL
if ($test$plusargs("dump")) begin
//$dumpvars(0, reality.rcp_0.if_logic);
//$dumpvars(0, reality.rcp_0.vclk_driver_0);
$dumpvars(0, reality.rcp_0.if_logic);
//$dumpvars(0, reality.rcp_0.ri_0);
//$dumpvars(0, reality.rcp_0.rsp_0_su );
//$dumpvars(0, reality.rcp_0.rsp_0_ls );
//$dumpvars(0, reality.rcp_0.rsp_0_io_logic );
//$dumpvars(0, reality.rcp_0.pi_0);
//$dumpvars(0, reality.rcp_0.rsp_0_io_logic );
//$dumpvars(0, reality.rcp_0.vi_0);
//$dumpvars(0, reality.rcp_0.left_pads.rac_0);
//$dumpvars(0, reality.rcp_0.rdp_0_tc_logic );
//$dumpvars(0, reality.rcp_0.rdp_0_ms_grp );
//$dumpvars(0, reality.rcp_0.rdp_0_tf_logic );
//$dumpvars(0, reality.rcp_0.rdp_0_tm_grp );
//$dumpvars(0, reality.rcp_0.rdp_0_cs_ew_cv );
//$dumpvars(0, reality.rcp_0.rdp_0_bl_logic );
//$dumpvars(0, reality.rcp_0.rdp_0_cc_logic );
$dumpvars(1, reality);
$dumpvars(1, reality.rcp_0);
end
if ($test$plusargs("rcp_dump")) $dumpvars(0, reality.rcp_0);
if ($test$plusargs("rcp_top_dump")) $dumpvars(1, reality.rcp_0);
if ($test$plusargs("vi_dump")) begin
$dumpvars(3, reality.rcp_0.vi_0);
//$dumpvars(0, reality.rcp_0.vi_0.vi_grp.vi_logic.clk_blk);
end
/*
if ($test$plusargs("ms_dump")) begin
$dumpvars(1, reality.rcp_0);
$dumpvars(0, reality.rcp_0.\rdp_0/memspan );
end
if ($test$plusargs("tc_dump")) begin
$dumpvars(1, reality.rcp_0);
$dumpvars(0, reality.rcp_0.\rdp_0/tc_logic );
end
*/
if ($test$plusargs("tst_dump")) $dumpvars(0, reality.rcp_0.if_logic);
`else
if ($test$plusargs("dump")) begin
$dumpvars(1, reality);
$dumpvars(1, reality.rcp_0);
$dumpvars(0, reality.rcp_0.pad_0);
$dumpvars(0, reality.rcp_0.rsp_0);
$dumpvars(0, reality.rcp_0.rdp_0);
$dumpvars(0, reality.rcp_0.mi_0);
$dumpvars(0, reality.rcp_0.pi_0);
$dumpvars(0, reality.rcp_0.si_0);
$dumpvars(0, reality.rcp_0.ai_0);
$dumpvars(0, reality.rcp_0.vi_0);
$dumpvars(0, reality.rcp_0.arb_0);
$dumpvars(0, reality.rcp_0.ri_0);
$dumpvars(0, reality.rcp_0.tst_0);
end
if ($test$plusargs("all_dump")) $dumpvars;
if ($test$plusargs("reality_top_dump")) $dumpvars(1, reality);
if ($test$plusargs("rcp_top_dump")) $dumpvars(1, reality.rcp_0);
if ($test$plusargs("rcp_dump")) $dumpvars(0, reality.rcp_0);
if ($test$plusargs("pad_dump")) $dumpvars(0, reality.rcp_0.pad_0);
if ($test$plusargs("rsp_dump")) $dumpvars(0, reality.rcp_0.rsp_0);
if ($test$plusargs("rdp_dump")) $dumpvars(0, reality.rcp_0.rdp_0);
if ($test$plusargs("rdp_top_dump")) $dumpvars(1, reality.rcp_0.rdp_0);
if ($test$plusargs("tc_dump")) $dumpvars(0, reality.rcp_0.rdp_0.tc);
if ($test$plusargs("mi_dump")) $dumpvars(0, reality.rcp_0.mi_0);
if ($test$plusargs("pi_dump")) $dumpvars(0, reality.rcp_0.pi_0);
if ($test$plusargs("si_dump")) $dumpvars(0, reality.rcp_0.si_0);
if ($test$plusargs("ai_dump")) $dumpvars(0, reality.rcp_0.ai_0);
if ($test$plusargs("vi_dump")) $dumpvars(3, reality.rcp_0.vi_0);
if ($test$plusargs("arb_dump")) $dumpvars(0, reality.rcp_0.arb_0);
if ($test$plusargs("ri_dump")) $dumpvars(0, reality.rcp_0.ri_0);
if ($test$plusargs("rac_dump")) $dumpvars(0, reality.rcp_0.pad_0.left_pads.rac_0);
if ($test$plusargs("pif_dump")) $dumpvars(0, reality.pif_0);
`endif
`ifdef RDRAM_0_PRESENT
if ($test$plusargs("rdram_dump")) $dumpvars(0, reality.rdram_0);
`endif
`ifdef RDRAM_1_PRESENT
if ($test$plusargs("rdram_dump")) $dumpvars(0, reality.rdram_1);
`endif
`ifdef ROM_0_PRESENT
if ($test$plusargs("rom_dump")) $dumpvars(0, reality.rom_0);
`endif
`ifdef ROM_1_PRESENT
if ($test$plusargs("rom_dump")) $dumpvars(0, reality.rom_1);
`endif
`ifdef GATE_LEVEL
`else
`ifdef IPC_PRESENT
if ($test$plusargs("ms_dump")) $dumpvars(0, reality.rcp_0.rdp_0.ms);
`endif
`endif
if ($getnum$plusarg("timelimit=", timelimit) == 1) $set_timelimit(timelimit);
end
// always @(reality.rcp_0.syn_clk) $display($time,, reality.rcp_0.syn_clk);
`ifdef IPC_PRESENT
initial
begin
if ($getstr$plusarg("vitab=", vifilename) == 1)
begin
if ($open_viout_file(vifilename) == -1)
begin
$write("Cannot open vi out file \n");
end
end
end
always @(posedge reality.rcp_0.vi_0.vclk)
begin
if ($output_vi(reality.rcp_0.vi_0.vbus_data, reality.rcp_0.vi_0.vbus_sync) == -1)
begin
$write("Cannot write vi output values \n");
end
end
`endif
initial begin
if ($test$plusargs("refresh")) begin
wait(reset_l);
wait(~reset_l);
wait(reset_l);
force reality.rcp_0.refresh_strobe = LOW;
forever begin
repeat (200) @(posedge clock);
force reality.rcp_0.refresh_strobe = HIGH;
@(posedge clock);
force reality.rcp_0.refresh_strobe = LOW;
end
end
end
`ifdef RSP_PRESENT
initial begin
if ($test$plusargs("load_dmem")) begin
$display("Loading DMEM ........");
`ifdef GATE_LEVEL
//from rcpgate_rsp_regr.h
`define DMEM_L reality.rcp_0.rsp_0_dmemx2_dmemLow
`define DMEM_H reality.rcp_0.rsp_0_dmemx2_dmemHigh
// $display(" You want me to load DMEM ??? Do it yourself");
$readmemh("SpData/d_0.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim7, 0);
$readmemh("SpData/d_1.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim6 , 0);
$readmemh("SpData/d_2.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim5 , 0);
$readmemh("SpData/d_3.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim4 , 0);
$readmemh("SpData/d_4.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim3 , 0);
$readmemh("SpData/d_5.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim2 , 0);
$readmemh("SpData/d_6.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim1 , 0);
$readmemh("SpData/d_7.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemHigh.ram_prim0 , 0);
$readmemh("SpData/d_8.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim7 , 0);
$readmemh("SpData/d_9.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim6 , 0);
$readmemh("SpData/d_a.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim5 , 0);
$readmemh("SpData/d_b.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim4 , 0);
$readmemh("SpData/d_c.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim3 , 0);
$readmemh("SpData/d_d.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim2 , 0);
$readmemh("SpData/d_e.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim1 , 0);
$readmemh("SpData/d_f.dhex",
reality.rcp_0.rsp_0_dmemx2_dmemLow.ram_prim0 , 0);
`else
$readmemh("SpData/d_0.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim7, 0);
$readmemh("SpData/d_1.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim6, 0);
$readmemh("SpData/d_2.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim5, 0);
$readmemh("SpData/d_3.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim4, 0);
$readmemh("SpData/d_4.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim3, 0);
$readmemh("SpData/d_5.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim2, 0);
$readmemh("SpData/d_6.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim1, 0);
$readmemh("SpData/d_7.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemHigh.ram_prim0, 0);
$readmemh("SpData/d_8.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim7, 0);
$readmemh("SpData/d_9.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim6, 0);
$readmemh("SpData/d_a.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim5, 0);
$readmemh("SpData/d_b.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim4, 0);
$readmemh("SpData/d_c.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim3, 0);
$readmemh("SpData/d_d.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim2, 0);
$readmemh("SpData/d_e.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim1, 0);
$readmemh("SpData/d_f.dhex",
reality.rcp_0.rsp_0.dmemx2.dmemLow.ram_prim0, 0);
`endif
end
end
initial begin
/* wait for reset to go away */
wait(`SYSTEM_READY);
/*
* wait additional cycles just to be sure.
* config_rdram should easily use up these cycles anyway
*/
repeat (4) @(posedge clock);
if ($test$plusargs("load_imem")) begin
$display($time," Loading IMEM ........");
`ifdef GATE_LEVEL
$readmemh("SpData/idata.ihex",
reality.rcp_0.rsp_0_imem.ram_prim , 0);
`else
$readmemh("SpData/idata.ihex",
reality.rcp_0.rsp_0.imem.ram_prim, 0);
`endif
end
end
`endif
initial begin
cycle_count = 0;
cyclelimit = 32'hfffffff0;
startdump = 32'hfffffff0;
if ($getnum$plusarg("cyclelimit=", cyclelimit) == 1)
begin
end
if ($getnum$plusarg("startdump=", startdump) == 1)
begin
$dumpoff;
$display("Dump=OFF (dump will be turned on at cycle 0x%h or %d)",
startdump, startdump);
end
forever @(posedge clock) begin
if (cycle_count === cyclelimit)
$finish;
else if (cycle_count == startdump) begin
$dumpon;
$display("Dump=ON");
end
cycle_count = cycle_count + 32'h1;
end
end
// Create reset for gate level memspan copy-load bus counter
//`ifdef GATE_LEVEL
//always @(reset_l) begin
// if (!reset_l) begin
// force reality.rcp_0.\rdp_0/memspan .\ms/rp/n6903 = 1;
// end
// else begin
// release reality.rcp_0.\rdp_0/memspan .\ms/rp/n6903 ;
// end
//end
//`endif
initial count = 0;
initial
begin
if ($test$plusargs("rambus_mon"))
begin
if ($getstr$plusarg("rambus_name=", rambus_fn) == 1)
tab_file_ptr = $fopen(rambus_fn);
else
tab_file_ptr = $fopen("rambus.tab");
forever @(reality.tx_clk)
begin
$fwrite(tab_file_ptr, "count: %d bus_data %h bus_ctrl %d bus_en %d", count, reality.bus_data, reality.bus_ctrl, reality.bus_enable);
$fdisplay(tab_file_ptr);
count = count + 1;
end
end
end
endmodule