Makefile
16.5 KB
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#!/usr/sbin/smake -J 4
###########################################################
#
# rules for extracting vectors from iosim/simv2.ipc
#
###########################################################
PRDEPTH = $(ROOT)/PR
include $(PRDEPTH)/PRdefs
include $(PRDEPTH)/PRrules
IOSIM = $(ROOT)/PR/iosim/src/iosim
TDXBIN = /hosts/kitana/ecad/attest/release/sgi_irix_33/bin
TDX_LSIM = $(TDXBIN)/tdx_lsim
SLOWIOSIM = $(IOSIM) -n $(BASE).slf \
-f $(IODIR)/$(BASE).tst \
-l $(SLOWDIR)/$(BASE).log \
-s "$(SIMVDIR)/simv2.ipc +ADDFLAGS \
+test_bypass \
+rcp_test_tssi \
+tssi_name=$(SLOWDIR)/$(BASE).slf"; \
SLOWEXECS = - cd $(DIRECTED); \
$(SLOWIOSIM) \
$(COMPACT) \
HPIOSIM = $(IOSIM) -n $(BASE).slf-hp \
-f $(IODIR)/$(BASE).tst \
-l $(HPDIR)/$(BASE).log \
-s "$(SIMVDIR)/simv2.ipc +ADDFLAGS \
+ignore_vbus \
+freeze_vclk_false \
+rcp_hp330_tssi \
+tssi_name=$(HPDIR)/$(BASE).slf";
HPEXECS = - cd $(DIRECTED); \
$(HPIOSIM) \
compress -f $(HPDIR)/$(BASE).slf \
BASE = `basename $@ | sed 's/\..*//'`
ATTEST = /hosts/sonya/d/tonyd/attest
VECDIR = /hosts/rayden/e/fault/vec
MODEL = $(ATTEST)/rcp_inner/rcp_inner
SLOWDIR = /hosts/rayden/e/fault/tssi_slow
HPDIR = /hosts/rayden/e/fault/tssi_hp
FULLDIR = /hosts/sonya/d/tonyd/tssi_full
SIMV = $(SIMVDIR)/simv2.ipc
LDIRT = ./*.rdram ./*.log ./*.tab ./*.rgb ./*.vec
DIRECTED = $(ROOT)/PR/iosim/data/directed
VECTOR_DIR = $(ROOT)/PR/hw2/chip/vector
IODIR = $(VECTOR_DIR)/io
ROM_DATA = $(DIRECTED)/rom_4.data \
$(DIRECTED)/rom_8.data
PIF_DATA = $(DIRECTED)/pif.data
TSSI2J971 = /hosts/sonya/d/tonyd/tssi_slow/tssi2j971
LVM_COMPRESS = /hosts/sonya/d/tonyd/tssi_slow/lvm_compress
# If you change this, change VCOMPACT also
COMPACT = $(TSSI2J971) $(@:.Z=); \
compress -f $(@:.Z=); \
$(LVM_COMPRESS) $(@:.slf.Z=.lvmadr); \
rm $(@:.slf.Z=.lvmadr); \
compress -f $(@:.slf.Z=C.lvmadr)
VCOMPACT = $(TSSI2J971) $(SLOWDIR)/$(@:.slow=.slf); \
compress -f $(SLOWDIR)/$(@:.slow=.slf); \
$(LVM_COMPRESS) $(SLOWDIR)/$(@:.slow=.lvmadr); \
rm $(SLOWDIR)/$(@:.slow=.lvmadr); \
compress -f $(SLOWDIR)/$(@:.slow=C.lvmadr)
default:
allhp: pi_vector.hp si_vector.hp ai_vector.hp mi_vector.hp viall_vector.hp
$(ROOT)/PR/iosim/src/iosim: $(_FORCE)
cd $(ROOT)/PR/iosim/src; make iosim
$(SIMVDIR)/simv2.ipc: $(_FORCE)
cd $(ROOT)/PR/hw2/chip/sim; make ipc
####################################################################################
# Targets for generation of Fault Grading Vector files
####################################################################################
############ PI
pi_v.vec: $(VECDIR)/pi/$$@
pi_v.tog: $(VECDIR)/pi/$$@
$(VECDIR)/pi/pi_v.vec: $(IODIR)/pi_v.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_v -f $(IODIR)/pi_v.tst -l $(IODIR)/pi_v_attest.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +mbus_mon \
+rcp_attest_tab +attest_name=$(VECDIR)/pi/pi_v.vec";
$(VECDIR)/pi/pi_v.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
pi_vector.vec: $(VECDIR)/pi/$$@
pi_vector.tog: $(VECDIR)/pi/$$@
$(VECDIR)/pi/pi_vector.vec: $(IODIR)/pi_vector.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_vector -f $(IODIR)/pi_vector.tst -l $(IODIR)/pi_vector_attest.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +mbus_mon \
+rcp_attest_tab +attest_name=$(VECDIR)/pi/pi_vector.vec";
$(VECDIR)/pi/pi_vector.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
pi_vector.slow: $(SLOWDIR)/pi_vector.slf.Z
$(SLOWDIR)/pi_vector.slf.Z: $(IODIR)/pi_vector.tst $(ROM_DATA)
$(SLOWEXECS:ADDFLAGS=load_rom)
pi_vector.hp: $(HPDIR)/pi_vector.slf.Z
$(HPDIR)/pi_vector.slf.Z: $(IODIR)/pi_vector.tst $(ROM_DATA)
$(HPEXECS:ADDFLAGS=load_rom)
############ SI
si_v.vec: $(VECDIR)/si/$$@
si_v.tog: $(VECDIR)/si/$$@
$(VECDIR)/si/si_v.vec: $(IODIR)/si_v.tst $(PIF_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n si_v -f $(IODIR)/si_v.tst -l $(IODIR)/si_v_attest.log \
-s "$(SIMVDIR)/simv2.ipc +load_pif +mbus_mon \
+rcp_attest_tab +attest_name=$(VECDIR)/si/si_v.vec";
$(VECDIR)/si/si_v.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
si_vector.vec: $(VECDIR)/si/$$@
si_vector.tog: $(VECDIR)/si/$$@
$(VECDIR)/si/si_vector.vec: $(IODIR)/si_vector.tst $(PIF_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n si_vector -f $(IODIR)/si_vector.tst -l $(IODIR)/si_vector_attest.log \
-s "$(SIMVDIR)/simv2.ipc +load_pif +mbus_mon \
+rcp_attest_tab +attest_name=$(VECDIR)/si/si_vector.vec";
$(VECDIR)/si/si_vector.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
si_vector.slow: $(SLOWDIR)/si_vector.slf.Z
$(SLOWDIR)/si_vector.slf.Z: $(IODIR)/si_vector.tst $(PIF_DATA)
$(SLOWEXECS:ADDFLAGS=load_pif)
si_vector.hp: $(HPDIR)/si_vector.slf.Z
$(HPDIR)/si_vector.slf.Z: $(IODIR)/si_vector.tst $(PIF_DATA)
$(HPEXECS:ADDFLAGS=load_pif)
############ AI
ai_v.vec: $(VECDIR)/ai/$$@
ai_v.tog: $(VECDIR)/ai/$$@
$(VECDIR)/ai/ai_v.vec: $(IODIR)/ai_v.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n ai_v -f $(IODIR)/ai_v.tst -l $(IODIR)/ai_v_attest.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +freeze_vclk_false \
+rcp_attest_tab +attest_name=$(VECDIR)/ai/ai_v.vec";
$(VECDIR)/ai/ai_v.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
ai_vector.vec: $(VECDIR)/ai/$$@
ai_vector.tog: $(VECDIR)/ai/$$@
$(VECDIR)/ai/ai_vector.vec: $(IODIR)/ai_vector.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n ai_vector -f $(IODIR)/ai_vector.tst -l $(IODIR)/ai_vector_attest.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +freeze_vclk_false \
+rcp_attest_tab +attest_name=$(VECDIR)/ai/ai_vector.vec";
$(VECDIR)/ai/ai_vector.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
ai_vector.slow: $(SLOWDIR)/ai_vector.slf.Z
$(SLOWDIR)/ai_vector.slf.Z: $(IODIR)/ai_vector.tst
$(SLOWEXECS:ADDFLAGS=freeze_vclk_false)
ai_vector.hp: $(HPDIR)/ai_vector.slf.Z
$(HPDIR)/ai_vector.slf.Z: $(IODIR)/ai_vector.tst
$(HPEXECS)
############ MI
mi_vector.vec: $(VECDIR)/mi/$$@
mi_vector.tog: $(VECDIR)/mi/$$@
$(VECDIR)/mi/mi_vector.vec: $(IODIR)/mi_vector.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n mi_vector -f $(IODIR)/mi_vector.tst -l $(IODIR)/mi_vector_attest.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +cbus_mon \
+rcp_attest_tab +attest_name=$(VECDIR)/mi/mi_vector.vec";
$(VECDIR)/mi/mi_vector.tog: $$(@:.tog=.vec)
$(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
mi_vector.slow: $(SLOWDIR)/mi_vector.slf.Z
$(SLOWDIR)/mi_vector.slf.Z: $(IODIR)/mi_vector.tst
$(SLOWEXECS:ADDFLAGS=cbus_mon)
mi_vector.hp: $(HPDIR)/mi_vector.slf.Z
$(HPDIR)/mi_vector.slf.Z: $(IODIR)/mi_vector.tst
$(HPEXECS:ADDFLAGS=cbus_mon)
############ VI
# VI section is at end of makefile
####################################################################################
# Targets for generation of older slow-speed test vector files
####################################################################################
pi_v.slf.Z: $(SLOWDIR)/pi_v.slf.Z
$(SLOWDIR)/pi_v.slf.Z: $(IODIR)/pi_v.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_v.slf -f $(IODIR)/pi_v.tst -l $(IODIR)/pi_v.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +test_bypass +mbus_mon \
+rcp_test_tssi +tssi_name=$(SLOWDIR)/pi_v.slf"; \
$(COMPACT)
si_v.slf.Z: $(SLOWDIR)/si_v.slf.Z
$(SLOWDIR)/si_v.slf.Z: $(IODIR)/si_v.tst $(PIF_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n si_v.slf -f $(IODIR)/si_v.tst -l $(IODIR)/si_v.log \
-s "$(SIMVDIR)/simv2.ipc +load_pif +test_bypass +mbus_mon \
+rcp_test_tssi +tssi_name=$(SLOWDIR)/si_v.slf"; \
$(COMPACT)
ai_v.slf.Z: $(SLOWDIR)/ai_v.slf.Z
$(SLOWDIR)/ai_v.slf.Z: $(IODIR)/ai_v.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n ai_v.slf -f $(IODIR)/ai_v.tst -l $(IODIR)/ai_v.log \
-s "$(SIMVDIR)/simv2.ipc +test_bypass +mbus_mon +freeze_vclk_false \
+rcp_test_tssi +tssi_name=$(SLOWDIR)/ai_v.slf"; \
$(COMPACT)
####################################################################################
# Targets for generation of full-speed test vector files
####################################################################################
$(FULLDIR)/pi_v.slf.Z: $(IODIR)/pi_v.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_v.slf-full-f $(IODIR)/pi_v.tst -l $(IODIR)/pi_v_full.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/pi_v.slf"; \
compress -f $(FULLDIR)/pi_v.slf
$(FULLDIR)/pi_vector.slf.Z: $(IODIR)/pi_vector.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_vector.slf-full -f $(IODIR)/pi_vector.tst -l $(IODIR)/pi_vector_full.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/pi_vector.slf"; \
compress -f $(FULLDIR)/pi_vector.slf
$(FULLDIR)/si_v.slf.Z: $(IODIR)/si_v.tst $(PIF_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n si_v.slf-full -f $(IODIR)/si_v.tst -l $(IODIR)/si_v_full.log \
-s "$(SIMVDIR)/simv2.ipc +load_pif +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/si_v.slf"; \
compress -f $(FULLDIR)/si_v.slf
$(FULLDIR)/ai_v.slf.Z: $(IODIR)/ai_v.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n ai_v.slf-full -f $(IODIR)/ai_v.tst -l $(IODIR)/ai_v_full.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/ai_v.slf"; \
compress -f $(FULLDIR)/ai_v.slf
$(FULLDIR)/viv_v.slf.Z: $(IODIR)/viv_v.full.tst $(IODIR)/viv_v.rdram.Z
uncompress -c $(IODIR)/viv_v.rdram.Z > $(IODIR)/viv_v.rdram; \
$(ROOT)/PR/iosim/src/iosim -m -n viv_v.slf-full -f $(IODIR)/viv_v.full.tst -l $(IODIR)/viv_v_full.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/viv_v.slf"; \
compress -f $(FULLDIR)/viv_v.slf
$(FULLDIR)/vih_v.slf.Z: $(IODIR)/vih_v.full.tst $(IODIR)/vih_v.rdram.Z
uncompress -c $(IODIR)/vih_v.rdram.Z > $(IODIR)/vih_v.rdram; \
$(ROOT)/PR/iosim/src/iosim -m -n vih_v.slf-full -f $(IODIR)/vih_v.full.tst -l $(IODIR)/vih_v_full.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +freeze_vclk_false \
+rcp_full_tssi +tssi_name=$(FULLDIR)/vih_v.slf"; \
compress -f $(FULLDIR)/vih_v.slf
####################################################################################
# Targets for generation of HP test vector files
####################################################################################
$(HPDIR)/pi_v.slf.Z: $(IODIR)/pi_v.tst $(ROM_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n pi_v.slf-hp -f $(IODIR)/pi_v.tst -l $(IODIR)/pi_v_hp.log \
-s "$(SIMVDIR)/simv2.ipc +load_rom +mbus_mon +ignore_vbus +freeze_vclk_false \
+rcp_hp330_tssi +tssi_name=$(HPDIR)/pi_v.slf"; \
compress -f $(HPDIR)/pi_v.slf
$(HPDIR)/si_v.slf.Z: $(IODIR)/si_v.tst $(PIF_DATA)
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n si_v.slf-hp -f $(IODIR)/si_v.tst -l $(IODIR)/si_v_hp.log \
-s "$(SIMVDIR)/simv2.ipc +load_pif +mbus_mon +ignore_vbus +freeze_vclk_false \
+rcp_hp330_tssi +tssi_name=$(HPDIR)/si_v.slf"; \
compress -f $(HPDIR)/si_v.slf
$(HPDIR)/ai_v.slf.Z: $(IODIR)/ai_v.tst
- cd $(DIRECTED); \
$(ROOT)/PR/iosim/src/iosim -n ai_v.slf-hp -f $(IODIR)/ai_v.tst -l $(IODIR)/ai_v_hp.log \
-s "$(SIMVDIR)/simv2.ipc +mbus_mon +ignore_vbus +freeze_vclk_false \
+rcp_hp330_tssi +tssi_name=$(HPDIR)/ai_v.slf"; \
compress -f $(HPDIR)/ai_v.slf
####################################################################################
# Targets for generation of new vi tests
####################################################################################
# global vi test setup
MONITOR = $(ROOT)/PR/rdpsim/backend/monitor -i $(BASE).tab -o $(BASE).rgb
UNCOMPRESS = uncompress -c random.rdram.Z > $(IODIR)/$(BASE).rdram
IOSIMFLAGS = -n $(BASE) -f $(IODIR)/$(BASE).tst -l $(IODIR)/$(BASE)_attest.log
LOGARGS = # +vi_all_dump -vcd /d/kluster/vi.dump
SIMVFLAGS = "$(SIMV) $(LOGARGS) +vitab=$(BASE).tab +rcp_attest_tab \
+attest_name=$(VECDIR)/vi/$@ \
+mbus_mon +mmap_rdram=$(IODIR)/$(BASE) +freeze_vectorclk_false"
VIVECDEPENDS = $(IODIR)/$$(@:.vec=).tst random.rdram.Z
VITOGDEPENDS = $(VECDIR)/vi/$$(@:.tog=.vec)
VIVECCOMMANDS = $(UNCOMPRESS); \
$(IOSIM) $(IOSIMFLAGS) -s $(SIMVFLAGS);
VITOGCOMMANDS = $(TDX_LSIM) $(MODEL) -vector_file $? -log_file $(?:.vec=.lsimlog) \
-outmodel $(@:.tog=) -init_file ../rcp_inner.tdxinit
SLOWFLAGS = -n $(BASE).slf -f $(IODIR)/$(BASE).tst -l $(SLOWDIR)/$(BASE).log
SLOWSIMV = "$(SIMV) +test_bypass +mbus_mon \
+mmap_rdram=$(IODIR)/$(BASE) +freeze_vclk_false \
+rcp_test_tssi +tssi_name=$(SLOWDIR)/$(BASE).slf"
SLOWDPDS = $(IODIR)/$$(@:.slow=).tst random.rdram.Z
SLOWCMDS = $(UNCOMPRESS); \
$(IOSIM) $(SLOWFLAGS) -s $(SLOWSIMV); \
$(VCOMPACT);
###################################################################################
# 32 bit, 640x4 NTSC LAN2
vih32_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
$(MONITOR) -h 0x004402c4 -v 0x00010009
vih32_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# 18 bit, 32x120 NTSC HAN1
viv18_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
$(MONITOR) -h 0x00200040 -v 0x000500f5
viv18_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# 18 bit, 640x4 PAL HAF1
vih18_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
$(MONITOR) -h 0x004a02ca -v 0x00010009
vih18_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# test 1, HPN2, LPN1, LPF2, HPF1, LAF1
vic01_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
vic01_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# test 2, HPN1, LPN2, LAN1, LAF2
vic02_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
vic02_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# test 3, LAN1 with random X/Y scale changes
vic03_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
vic03_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# Random test. Writes of random data to vi registers
virnd_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
virnd_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# Span buffer test.
vispn_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
$(MONITOR) -h 0x00200040 -v 0x00050025
vispn_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
# Combination of 8 primary tests
viall_vector.vec: $(VIVECDEPENDS)
$(VIVECCOMMANDS)
viall_vector.tog: $(VITOGDEPENDS)
$(VITOGCOMMANDS)
viall_vector.slow: $(SLOWDPDS)
$(SLOWCMDS)
viall_vector.hp: $(HPDIR)/viall_vector.slf.Z
$(HPDIR)/viall_vector.slf.Z: $(IODIR)/viall_vector.tst
$(HPEXECS:ADDFLAGS=mmap_rdram=viall_vector)