# original manufacturing test vector tests

# SU	PR/hw2/chip/vector/rsp/suctl/issue1.s
# SU	PR/hw2/chip/vector/rsp/suctl/issue2.s
# SU	PR/hw2/chip/vector/rsp/sudp/sudp.s
# SU	PR/hw2/chip/vector/rsp/sudp/surf.s
# SU	PR/hw2/chip/vector/rsp/ls/ldv1.s
# SU	PR/hw2/chip/vector/rsp/ls/ldv2.s
# SU	PR/hw2/chip/vector/rsp/ls/fldv1.s
# SU	PR/hw2/chip/vector/rsp/ls/fldv2.s
# SU    PR/hw2/chip/vector/rsp/ls/zldv1.s
# SU    PR/hw2/chip/vector/rsp/ls/zldv2.s
# SU	PR/hw2/chip/vector/rsp/ls/lsmisc1.s
# SU	PR/hw2/chip/vector/rsp/ls/lsmisc2.s
# SU	PR/hw2/chip/vector/rsp/ls/lsmisc3.s
# SU	PR/hw2/chip/vector/rsp/ls/sdv1.s
# SU	PR/hw2/chip/vector/rsp/ls/sdv2.s
# SU	PR/hw2/chip/vector/rsp/ls/sdv3.s
# SU	PR/hw2/chip/vector/rsp/ls/sdv4.s
# SU	PR/hw2/chip/vector/rsp/ls/mtc2.s
# SU	PR/hw2/chip/vector/rsp/dmem/dmem_1.s
# SU	PR/hw2/chip/vector/rsp/dmem/dmem_2.s
# SU	PR/hw2/chip/vector/rsp/dmem/dmem_3.s
# SU	PR/hw2/chip/vector/rsp/dmem/dmem_4.s
# SU	PR/hw2/chip/vector/rsp/dmem/dmem_5.s
#
# VU	PR/hw2/chip/vector/rsp/vurf/vurf.s
# VU	PR/hw2/chip/vector/rsp/vurf/vurf1.s
# VU	PR/hw2/chip/vector/rsp/divrom/divrom.s
# VU	PR/hw2/chip/vector/rsp/divctl/divctl.in
# VU	PR/hw2/chip/vector/rsp/vudp/vau.in
# VU	PR/hw2/chip/vector/rsp/vudp/vb.in
# VU	PR/hw2/chip/vector/rsp/vudp/vlu.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmsc.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu1.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu2.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu3.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu4.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu5.in
# VU	PR/hw2/chip/vector/rsp/vudp/vmu6.in
#
# DMA	PR/hw2/chip/vector/rsp/dma/dma80_vector.s

	
######################################################################
	
# testsuite for tests based on gng failures

# These are the bad01 and bad02 tests
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm00.s
# SU      PR/hw2/chip/vector/rsp/from_gng/iltest14.s
# VU      PR/hw2/chip/vector/rsp/from_gng/vcl_v.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacf_q.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmadl_h.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vrndn_h.in

# All of the tests that the 10 bad RSP's fail
# SU      PR/hw2/chip/vector/rsp/from_gng/add1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/add2.s
# SU      PR/hw2/chip/vector/rsp/from_gng/addu1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/addu2.s
# SU      PR/hw2/chip/vector/rsp/from_gng/bgezal1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/bltzal1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/bptest2.s
# SU      PR/hw2/chip/vector/rsp/from_gng/bptest3.s
# SU      PR/hw2/chip/vector/rsp/from_gng/ctc21.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm01.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm02.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm03.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm10.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm11.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm12.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm13.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm20.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm21.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm22.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm23.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm30.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm31.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm32.s
# SU      PR/hw2/chip/vector/rsp/from_gng/di_norm33.s
# SU      PR/hw2/chip/vector/rsp/from_gng/iltest11.s
# SU      PR/hw2/chip/vector/rsp/from_gng/iltest18.s
# SU      PR/hw2/chip/vector/rsp/from_gng/iltest20.s
# SU      PR/hw2/chip/vector/rsp/from_gng/iltest24.s
# SU      PR/hw2/chip/vector/rsp/from_gng/jal1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/nor1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/ori1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sb1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sh1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sra1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/srav1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sub1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sub2.s
# SU      PR/hw2/chip/vector/rsp/from_gng/subu1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/subu2.s
# SU      PR/hw2/chip/vector/rsp/from_gng/sw1.s
# VU      PR/hw2/chip/vector/rsp/from_gng/vch_v.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vcr_v.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacf_h.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacf_v.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacf_w.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacu_h.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacu_q.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacu_v.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmacu_w.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmadm_h.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmadm_v1.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmadn_h.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vmadn_w.in
# VU      PR/hw2/chip/vector/rsp/from_gng/vrndn_q.in
# SU      PR/hw2/chip/vector/rsp/from_gng/xor1.s
# SU      PR/hw2/chip/vector/rsp/from_gng/xori1.s

####################################################################

# New set of extensive rsp vectors, all of the original series that
# made sense to port into test vectors

SU	PR/rspsim/bpregre/ready/bpmult.s
SU	PR/rspsim/bpregre/ready/bptest0.s
SU	PR/rspsim/bpregre/ready/bptest1.s
SU	PR/rspsim/bpregre/ready/bptest2.s
SU	PR/rspsim/bpregre/ready/bptest3.s
SU	PR/rspsim/bpregre/ready/bptest4.s
SU      PR/rspsim/diregre/ready/di_ctlhz000.s
SU      PR/rspsim/diregre/ready/di_ctlhz001.s
SU      PR/rspsim/diregre/ready/di_ctlhz002.s
SU      PR/rspsim/diregre/ready/di_ctlhz010.s

SU      PR/rspsim/diregre/ready/di_ctlhz011.s
SU      PR/rspsim/diregre/ready/di_ctlhz012.s
SU      PR/rspsim/diregre/ready/di_ctlhz100.s
SU      PR/rspsim/diregre/ready/di_ctlhz101.s
SU      PR/rspsim/diregre/ready/di_ctlhz102.s
SU      PR/rspsim/diregre/ready/di_ctlhz110.s
SU      PR/rspsim/diregre/ready/di_ctlhz111.s
SU      PR/rspsim/diregre/ready/di_ctlhz112.s
SU      PR/rspsim/diregre/ready/di_ldst00.s
SU      PR/rspsim/diregre/ready/di_ldst01.s

SU      PR/rspsim/diregre/ready/di_ldst10.s
SU      PR/rspsim/diregre/ready/di_ldst20.s
# SU      PR/rspsim/diregre/ready/di_reg.s
SU      PR/rspsim/diregre/ready/di_reghz0.s
SU      PR/rspsim/diregre/ready/di_reghz1.s
SU      PR/rspsim/diregre/ready/di_reghz2.s
SU      PR/rspsim/diregre/ready/di_reghz3.s
SU	PR/rspsim/ilregre/ready/iltest1.s
SU	PR/rspsim/ilregre/ready/iltest10.s
SU	PR/rspsim/ilregre/ready/iltest11.s

SU	PR/rspsim/ilregre/ready/iltest12.s
SU	PR/rspsim/ilregre/ready/iltest13.s
SU	PR/rspsim/ilregre/ready/iltest14.s
SU	PR/rspsim/ilregre/ready/iltest15.s
SU	PR/rspsim/ilregre/ready/iltest16.s
SU	PR/rspsim/ilregre/ready/iltest17.s
SU	PR/rspsim/ilregre/ready/iltest18.s
SU	PR/rspsim/ilregre/ready/iltest19.s
SU	PR/rspsim/ilregre/ready/iltest2.s
SU	PR/rspsim/ilregre/ready/iltest20.s
SU	PR/rspsim/ilregre/ready/iltest21.s
SU	PR/rspsim/ilregre/ready/iltest22.s
SU	PR/rspsim/ilregre/ready/iltest23.s
SU	PR/rspsim/ilregre/ready/iltest24.s
SU	PR/rspsim/ilregre/ready/iltest25.s
SU	PR/rspsim/ilregre/ready/iltest3.s
SU	PR/rspsim/ilregre/ready/iltest4.s
SU	PR/rspsim/ilregre/ready/iltest5.s
SU	PR/rspsim/ilregre/ready/iltest6.s
SU	PR/rspsim/ilregre/ready/iltest7.s
SU	PR/rspsim/ilregre/ready/iltest8.s
SU	PR/rspsim/ilregre/ready/iltest9.s
SU	PR/rspsim/suregre/ready/add1.s
SU	PR/rspsim/suregre/ready/addi1.s
SU	PR/rspsim/suregre/ready/addu2.s
SU	PR/rspsim/suregre/ready/and1.s
SU	PR/rspsim/suregre/ready/and2.s
SU	PR/rspsim/suregre/ready/beq1.s
SU	PR/rspsim/suregre/ready/bgez1.s
SU	PR/rspsim/suregre/ready/bgezal1.s
SU	PR/rspsim/suregre/ready/bgezal2.s
SU	PR/rspsim/suregre/ready/bgtz1.s
SU	PR/rspsim/suregre/ready/blez1.s
SU	PR/rspsim/suregre/ready/bltz1.s
SU	PR/rspsim/suregre/ready/bltzal1.s
SU	PR/rspsim/suregre/ready/bltzal2.s
SU	PR/rspsim/suregre/ready/bne1.s
SU	PR/rspsim/suregre/ready/cfc21.s
SU	PR/rspsim/suregre/ready/cfc22.s
SU	PR/rspsim/suregre/ready/ctc21.s
SU	PR/rspsim/suregre/ready/ctc22.s
SU	PR/rspsim/suregre/ready/init_regs.s
SU	PR/rspsim/suregre/ready/j1.s
SU	PR/rspsim/suregre/ready/jal1.s
SU	PR/rspsim/suregre/ready/jalr1.s
SU	PR/rspsim/suregre/ready/jr1.s
SU	PR/rspsim/suregre/ready/lb1.s
SU	PR/rspsim/suregre/ready/lbu1.s
SU	PR/rspsim/suregre/ready/lbv1.s
SU	PR/rspsim/suregre/ready/lbv2.s
SU	PR/rspsim/suregre/ready/lfv1.s
SU	PR/rspsim/suregre/ready/lh1.s
SU	PR/rspsim/suregre/ready/lhu1.s
SU	PR/rspsim/suregre/ready/lhv1.s
SU	PR/rspsim/suregre/ready/llv1.s
SU	PR/rspsim/suregre/ready/llv2.s
SU	PR/rspsim/suregre/ready/lpv1.s
SU	PR/rspsim/suregre/ready/lpv2.s
SU	PR/rspsim/suregre/ready/lqv1.s
SU	PR/rspsim/suregre/ready/lqv2.s
SU	PR/rspsim/suregre/ready/lrv1.s
SU	PR/rspsim/suregre/ready/lrv2.s
SU	PR/rspsim/suregre/ready/lsv1.s
SU	PR/rspsim/suregre/ready/lsv2.s
SU	PR/rspsim/suregre/ready/ltv1.s
SU	PR/rspsim/suregre/ready/lui1.s
SU	PR/rspsim/suregre/ready/luv1.s
SU	PR/rspsim/suregre/ready/luv2.s
SU	PR/rspsim/suregre/ready/lw1.s
SU	PR/rspsim/suregre/ready/mfc21.s
SU	PR/rspsim/suregre/ready/mfc22.s
SU	PR/rspsim/suregre/ready/mfc23.s
SU	PR/rspsim/suregre/ready/mfc24.s
SU	PR/rspsim/suregre/ready/mfc25.s
SU	PR/rspsim/suregre/ready/mfc26.s
SU	PR/rspsim/suregre/ready/mtc21.s
SU	PR/rspsim/suregre/ready/mtc22.s
SU	PR/rspsim/suregre/ready/mtc23.s
SU	PR/rspsim/suregre/ready/mtc24.s
SU	PR/rspsim/suregre/ready/mtc25.s
SU	PR/rspsim/suregre/ready/mtc26.s
SU	PR/rspsim/suregre/ready/nor1.s
SU	PR/rspsim/suregre/ready/nor2.s
SU	PR/rspsim/suregre/ready/or1.s
SU	PR/rspsim/suregre/ready/or2.s
SU	PR/rspsim/suregre/ready/sb1.s
SU	PR/rspsim/suregre/ready/sbv1.s
SU	PR/rspsim/suregre/ready/sbv2.s
SU	PR/rspsim/suregre/ready/sbv3.s
SU	PR/rspsim/suregre/ready/sbv4.s
SU	PR/rspsim/suregre/ready/sfv1.s
SU	PR/rspsim/suregre/ready/sfv2.s
SU	PR/rspsim/suregre/ready/sh1.s
SU	PR/rspsim/suregre/ready/shv1.s
SU	PR/rspsim/suregre/ready/shv2.s
SU	PR/rspsim/suregre/ready/sll1.s
SU	PR/rspsim/suregre/ready/sllv1.s
SU	PR/rspsim/suregre/ready/sllv2.s
SU	PR/rspsim/suregre/ready/slt1.s
SU	PR/rspsim/suregre/ready/slt2.s
SU	PR/rspsim/suregre/ready/sltu1.s
SU	PR/rspsim/suregre/ready/sltu2.s
SU	PR/rspsim/suregre/ready/slv1.s
SU	PR/rspsim/suregre/ready/slv2.s
SU	PR/rspsim/suregre/ready/slv3.s
SU	PR/rspsim/suregre/ready/slv4.s
SU	PR/rspsim/suregre/ready/spv1.s
SU	PR/rspsim/suregre/ready/spv2.s
SU	PR/rspsim/suregre/ready/spv3.s
SU	PR/rspsim/suregre/ready/spv4.s
SU	PR/rspsim/suregre/ready/sqv1.s
SU	PR/rspsim/suregre/ready/sqv2.s
SU	PR/rspsim/suregre/ready/sqv3.s
SU	PR/rspsim/suregre/ready/sqv4.s
SU	PR/rspsim/suregre/ready/sra1.s
SU	PR/rspsim/suregre/ready/srav1.s
SU	PR/rspsim/suregre/ready/srav2.s
SU	PR/rspsim/suregre/ready/srl1.s
SU	PR/rspsim/suregre/ready/srlv1.s
SU	PR/rspsim/suregre/ready/srlv2.s
SU	PR/rspsim/suregre/ready/srv1.s
SU	PR/rspsim/suregre/ready/srv2.s
SU	PR/rspsim/suregre/ready/srv3.s
SU	PR/rspsim/suregre/ready/srv4.s
SU	PR/rspsim/suregre/ready/ssv1.s
SU	PR/rspsim/suregre/ready/ssv2.s
SU	PR/rspsim/suregre/ready/ssv3.s
SU	PR/rspsim/suregre/ready/ssv4.s
SU	PR/rspsim/suregre/ready/stv1.s
SU	PR/rspsim/suregre/ready/sub1.s
SU	PR/rspsim/suregre/ready/subu2.s
SU	PR/rspsim/suregre/ready/suv1.s
SU	PR/rspsim/suregre/ready/suv2.s
SU	PR/rspsim/suregre/ready/suv3.s
SU	PR/rspsim/suregre/ready/suv4.s
SU	PR/rspsim/suregre/ready/sw1.s
SU	PR/rspsim/suregre/ready/swv1.s
SU	PR/rspsim/suregre/ready/xor1.s
SU	PR/rspsim/suregre/ready/xor2.s
VU	PR/rspsim/vuregre/src/dp_mul/dp_mul1.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_mix.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_neg.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_chain_pos.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_mix.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_neg.in
VU	PR/rspsim/vuregre/src/dp_recp/dp_recp_pos.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_mix.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_neg.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_chain_pos.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_mix.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_neg.in
VU	PR/rspsim/vuregre/src/dp_sqrt/dp_sqrt_pos.in
VU	PR/rspsim/vuregre/src/sp_recp/sp_recp_mix.in
VU	PR/rspsim/vuregre/src/sp_recp/sp_recp_neg.in
VU	PR/rspsim/vuregre/src/sp_recp/sp_recp_pos.in
VU	PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_mix.in
VU	PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_neg.in
VU	PR/rspsim/vuregre/src/sp_sqrt/sp_sqrt_pos.in
VU	PR/rspsim/vuregre/src/vabs/vabs_v.in
VU	PR/rspsim/vuregre/src/vadd/vadd_v.in
VU	PR/rspsim/vuregre/src/vaddc/vaddc_v.in
VU	PR/rspsim/vuregre/src/vch/vch_v.in
VU	PR/rspsim/vuregre/src/vcl/vcl_v.in
VU	PR/rspsim/vuregre/src/vcr/vcr_v.in
VU	PR/rspsim/vuregre/src/veq/veq_v.in
VU	PR/rspsim/vuregre/src/vge/vge_v.in
VU	PR/rspsim/vuregre/src/vge_dbl/vge_dbl_v.in
VU	PR/rspsim/vuregre/src/vlog/vand.in
VU	PR/rspsim/vuregre/src/vlog/vnand.in
VU	PR/rspsim/vuregre/src/vlog/vnor.in
VU	PR/rspsim/vuregre/src/vlog/vor.in
VU	PR/rspsim/vuregre/src/vlog/vxnor.in
VU	PR/rspsim/vuregre/src/vlog/vxor.in
VU	PR/rspsim/vuregre/src/vlt/vlt_v.in
VU	PR/rspsim/vuregre/src/vlt_dbl/vlt_dbl_v.in
VU	PR/rspsim/vuregre/src/vmacf/vmacf_clamp.in
VU	PR/rspsim/vuregre/src/vmacf/vmacf_v.in
VU	PR/rspsim/vuregre/src/vmacq/vmacq_v.in
VU	PR/rspsim/vuregre/src/vmacq/vmacq_v1.in
VU	PR/rspsim/vuregre/src/vmacq/vmacq_v2.in
VU	PR/rspsim/vuregre/src/vmacu/vmacu_clamp.in
VU	PR/rspsim/vuregre/src/vmacu/vmacu_v.in
VU	PR/rspsim/vuregre/src/vmadh/vmadh_clamp.in
VU	PR/rspsim/vuregre/src/vmadh/vmadh_v.in
VU	PR/rspsim/vuregre/src/vmadh/vmadh_v1.in
VU	PR/rspsim/vuregre/src/vmadh1/vmadh1_v.in
VU	PR/rspsim/vuregre/src/vmadl/vmadl_clamp.in
VU	PR/rspsim/vuregre/src/vmadl/vmadl_v.in
VU	PR/rspsim/vuregre/src/vmadm/vmadm_clamp.in
VU	PR/rspsim/vuregre/src/vmadm/vmadm_v.in
VU	PR/rspsim/vuregre/src/vmadm/vmadm_v1.in
VU	PR/rspsim/vuregre/src/vmadn/vmadn_clamp.in
VU	PR/rspsim/vuregre/src/vmadn/vmadn_v.in
VU	PR/rspsim/vuregre/src/vmadn/vmadn_v1.in
VU	PR/rspsim/vuregre/src/vmov/vmov.in
VU	PR/rspsim/vuregre/src/vmrg/vmrg_v.in
VU	PR/rspsim/vuregre/src/vmudh/vmudh_v.in
VU	PR/rspsim/vuregre/src/vmudh/vmudh_v1.in
VU	PR/rspsim/vuregre/src/vmudh1/vmudh1_v.in
VU	PR/rspsim/vuregre/src/vmudl/vmudl_v.in
VU	PR/rspsim/vuregre/src/vmudl/vmudl_v1.in
VU	PR/rspsim/vuregre/src/vmudm/vmudm_v.in
VU	PR/rspsim/vuregre/src/vmudm/vmudm_v1.in
VU	PR/rspsim/vuregre/src/vmudn/vmudn_v.in
VU	PR/rspsim/vuregre/src/vmudn/vmudn_v1.in
VU	PR/rspsim/vuregre/src/vmulf/vmulf_v.in
VU	PR/rspsim/vuregre/src/vmulf/vmulf_v1.in
VU	PR/rspsim/vuregre/src/vmulq/vmulq_v.in
VU	PR/rspsim/vuregre/src/vmulu/vmulu_v.in
VU	PR/rspsim/vuregre/src/vmulu/vmulu_v1.in
VU	PR/rspsim/vuregre/src/vne/vne_v.in
VU	PR/rspsim/vuregre/src/vne_dbl/vne_dbl_v.in
VU	PR/rspsim/vuregre/src/vrndn/vrndn_v.in
VU	PR/rspsim/vuregre/src/vrndn/vrndn_v1.in
VU	PR/rspsim/vuregre/src/vrndp/vrndp_v.in
VU	PR/rspsim/vuregre/src/vrndp/vrndp_v1.in
VU	PR/rspsim/vuregre/src/vsaw/vsaw.in
VU	PR/rspsim/vuregre/src/vsub/vsub_v.in
VU	PR/rspsim/vuregre/src/vsubc/vsubc_h.in
VU	PR/rspsim/vuregre/src/vsubc/vsubc_q.in
VU	PR/rspsim/vuregre/src/vsubc/vsubc_v.in
VU	PR/rspsim/vuregre/src/vsubc/vsubc_w.in

####################################################################

# second set of extensive rsp vectors, all of the remaining h,q,w
# vectors that weren't included in the batch above

VU	PR/rspsim/vuregre/src/vabs/vabs_h.in 
VU	PR/rspsim/vuregre/src/vabs/vabs_q.in 
VU	PR/rspsim/vuregre/src/vabs/vabs_w.in 
VU	PR/rspsim/vuregre/src/vadd/vadd_h.in 
VU	PR/rspsim/vuregre/src/vadd/vadd_q.in 
VU	PR/rspsim/vuregre/src/vadd/vadd_w.in 
VU	PR/rspsim/vuregre/src/vaddc/vaddc_h.in 
VU	PR/rspsim/vuregre/src/vaddc/vaddc_q.in 
VU	PR/rspsim/vuregre/src/vaddc/vaddc_w.in 
VU	PR/rspsim/vuregre/src/veq/veq_h.in 
VU	PR/rspsim/vuregre/src/veq/veq_q.in 
VU	PR/rspsim/vuregre/src/veq/veq_w.in 
VU	PR/rspsim/vuregre/src/vge/vge_h.in 
VU	PR/rspsim/vuregre/src/vge/vge_q.in 
VU	PR/rspsim/vuregre/src/vge/vge_w.in 
VU	PR/rspsim/vuregre/src/vlt/vlt_h.in 
VU	PR/rspsim/vuregre/src/vlt/vlt_q.in 
VU	PR/rspsim/vuregre/src/vlt/vlt_w.in 
VU	PR/rspsim/vuregre/src/vmacf/vmacf_h.in 
VU	PR/rspsim/vuregre/src/vmacf/vmacf_q.in 
VU	PR/rspsim/vuregre/src/vmacf/vmacf_w.in 
VU	PR/rspsim/vuregre/src/vmacu/vmacu_h.in 
VU	PR/rspsim/vuregre/src/vmacu/vmacu_q.in 
VU	PR/rspsim/vuregre/src/vmacu/vmacu_w.in 
VU	PR/rspsim/vuregre/src/vmadh/vmadh_h.in 
VU	PR/rspsim/vuregre/src/vmadh/vmadh_q.in 
VU	PR/rspsim/vuregre/src/vmadh/vmadh_w.in 
VU	PR/rspsim/vuregre/src/vmadh1/vmadh1_h.in 
VU	PR/rspsim/vuregre/src/vmadh1/vmadh1_q.in 
VU	PR/rspsim/vuregre/src/vmadh1/vmadh1_w.in 
VU	PR/rspsim/vuregre/src/vmadl/vmadl_h.in 
VU	PR/rspsim/vuregre/src/vmadl/vmadl_q.in 
VU	PR/rspsim/vuregre/src/vmadl/vmadl_w.in 
VU	PR/rspsim/vuregre/src/vmadm/vmadm_h.in 
VU	PR/rspsim/vuregre/src/vmadm/vmadm_q.in 
VU	PR/rspsim/vuregre/src/vmadm/vmadm_w.in 
VU	PR/rspsim/vuregre/src/vmadn/vmadn_h.in 
VU	PR/rspsim/vuregre/src/vmadn/vmadn_q.in 
VU	PR/rspsim/vuregre/src/vmadn/vmadn_w.in 
VU	PR/rspsim/vuregre/src/vmrg/vmrg_h.in 
VU	PR/rspsim/vuregre/src/vmrg/vmrg_q.in 
VU	PR/rspsim/vuregre/src/vmrg/vmrg_w.in 
VU	PR/rspsim/vuregre/src/vmudh/vmudh_h.in 
VU	PR/rspsim/vuregre/src/vmudh/vmudh_q.in 
VU	PR/rspsim/vuregre/src/vmudh/vmudh_w.in 
VU	PR/rspsim/vuregre/src/vmudh1/vmudh1_h.in 
VU	PR/rspsim/vuregre/src/vmudh1/vmudh1_q.in 
VU	PR/rspsim/vuregre/src/vmudh1/vmudh1_w.in 
VU	PR/rspsim/vuregre/src/vmudl/vmudl_h.in 
VU	PR/rspsim/vuregre/src/vmudl/vmudl_q.in 
VU	PR/rspsim/vuregre/src/vmudl/vmudl_w.in 
VU	PR/rspsim/vuregre/src/vmudm/vmudm_h.in 
VU	PR/rspsim/vuregre/src/vmudm/vmudm_q.in 
VU	PR/rspsim/vuregre/src/vmudm/vmudm_w.in 
VU	PR/rspsim/vuregre/src/vmudn/vmudn_h.in 
VU	PR/rspsim/vuregre/src/vmudn/vmudn_q.in 
VU	PR/rspsim/vuregre/src/vmudn/vmudn_w.in 
VU	PR/rspsim/vuregre/src/vmulf/vmulf_h.in 
VU	PR/rspsim/vuregre/src/vmulf/vmulf_q.in 
VU	PR/rspsim/vuregre/src/vmulf/vmulf_w.in 
VU	PR/rspsim/vuregre/src/vmulu/vmulu_h.in 
VU	PR/rspsim/vuregre/src/vmulu/vmulu_q.in 
VU	PR/rspsim/vuregre/src/vmulu/vmulu_w.in 
VU	PR/rspsim/vuregre/src/vne/vne_h.in 
VU	PR/rspsim/vuregre/src/vne/vne_q.in 
VU	PR/rspsim/vuregre/src/vne/vne_w.in 
VU	PR/rspsim/vuregre/src/vrndn/vrndn_h.in 
VU	PR/rspsim/vuregre/src/vrndn/vrndn_q.in 
VU	PR/rspsim/vuregre/src/vrndn/vrndn_w.in 
VU	PR/rspsim/vuregre/src/vrndp/vrndp_h.in 
VU	PR/rspsim/vuregre/src/vrndp/vrndp_q.in 
VU	PR/rspsim/vuregre/src/vrndp/vrndp_w.in 
VU	PR/rspsim/vuregre/src/vsub/vsub_h.in 
VU	PR/rspsim/vuregre/src/vsub/vsub_q.in 
VU	PR/rspsim/vuregre/src/vsub/vsub_w.in 

## Added in just to be safe
SU      PR/hw2/chip/vector/rsp/from_gng/ori1.s
SU      PR/hw2/chip/vector/rsp/from_gng/xori1.s