asicsyn_quick_reference
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ASIC Synthesizer Quick Reference
--------------------------------
Created: 6/8/94
This is an abbreviated summary of all the "useful" commands to the ASIC
Synthesizer. Other commands are available, RTFM (read the fine manual).
##############################################
# Setting the Synthesis environment #
##############################################
show environment - to check the values
set process slow
set temperature 110
set vddlevel 2.7
set predcapacitance 0.03*nbPins + 0.13 pf
Note: the Makefile should provide a standard asicsyn_defaults.cmd
which will set these variables automatically.
##############################################
# Loading designs #
##############################################
load [v]design_name - explicitly loads the Verilog
load design_name - uses the default types
Note: the second form "load design_name" will load any [nls]
version of the cell before the [v]. Be explicit about
what you want. Also, ASICsyn will load any other cells
it needs by default, so be careful about loading sub-cells.
##############################################
# Design specifc synthesis controls #
##############################################
set cell cell_name - synthesis will only work on this cell and
and sub-cells below it.
set frozen cell_name(s) - synthesis will not work on this cell, you
must already have a synthesized or loaded
a netlist for this cell.
expandinst inst_name - flattens the instance hierarchy into the
current cell. (one level)
flatteninst inst_name new_cell - flattens the instance hierarchy into the
new cell. (all levels, creates a new cell)
flattencell new_cell - flattens the current cell hierarchy completely into
the new cell. (all levels, creates a new cell)
isolate [option] inst_name [suffix] - makes a unique cell for the instance.
the new cell name has the added suffix.
[option] = hierarchy (RTFM)
show optimization - to check the control values
set default cpueffort {1(low), 2(med), 3(high), or manual}
Note: set the cpueffort to manual to use any of the following:
set default flattening {low, medium, high, or none}
set default minimization {low, medium, high, or none}
set default factorization {low, medium, high, or none}
##############################################
# Design specifc constraints #
##############################################
set maxrampdelay 2.0 - max. net rise/fall time
set maxcapacitance 2.0 - max. net capacitance
set maxfanout 10 - max. net fanout
set maxcellcapacitance 1.0 cell_name(s) - max. capacitance on the
cell outputs.
show constraints - to check the constraint values
set frequency 65 clk
set setup 2.0 in_name --> clk
set outdelay 6.0 clk --> out_name
set maxdelay 14.0 in_name --> out_name
set stable pin_name
set clockdrive 0.0
set drive [rising|falling] 1.0 in_name
set load 2.0 out_name(s)
set inputdelay [rising|falling] 1.0 in_name(s)
set break inst.in_pin --> inst.out_pin
##############################################
# Commands that do the synthesis #
##############################################
synthesize - turns Verilog into equations
optimize - turns equations into gates
speedup {# or *} - iterates # times to speed up the gates
##############################################
# Saving results and reporting #
##############################################
write - writes out [nls] files, each subcell
report {area, timing, longtiming, designrules, or longdesignrules}