toolTips
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No _ in instance names. (Compass)
No caps in module names. (Verilog into Compass)
Re. case insensitivity: it's not. Make signal names lower case.
Unique 2-letter prefix on module names because Verilog is flat. (Ken H)
Verilog module libraries
`include "xxx" xxx is:
for ASIC synthesizer built-ins:
/hosts/sonya/usr/ecad/compass/v8r4.6/etc/aslib.v
for DP modules derived from schmeatics:
in Compass text window:
in browser choose library vlogdp010d (or other current vers.)
in browser, from vlogdp010d, choose [v].....
load! it
file -> write it
This leaves an ASCII version in the local directory, which
you can `include.
for standard cell modules derived from schematics:
??? should be something similar to the datapath scenario
Source code for Verilog requires `includes for lower levels of heirarchy and
library modules. These must be commented out for Compass ASICsynthesis. Is
there a way with command line options, ifdefs, makefiles ... to use identical
source for both?
Compass
to produce do
portable netlist in logicAsst: commands->set pcl
dppcl_p.nls click on pcl
set Layout_Option to Portable
commands->compile->simulation
click on pcl
gate-level layout model netlist in logicAsst: commands->set pcl
dppcl_l.nls click on pcl
set Layout_Option to Optimized
commands->compile->simulation
click on pcl
Liz Chambers, Nancy Gomes Compass: 408-383-4720
Compass Hot Line: 800-937-8574
Compass Configuration Names for hotline:
silicon_nint_2sg
silicon_nint_4sg