wireDelays
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--- Forwarded mail from "Matt Rohm" <rohm@cayman>
To: hayes@arakis (Ken Hayes), kw@cayman, doherty@cayman
Cc: pg@cayman
I looked up some numbers for wire resistance and capacitance from the
NEC process tables. It is difficult to boil it down to one number, but
here goes...
A simplified model for the delay of the wire is composed of:
- RC delay of the wire
- Additional capacitive loading on the driver
NEC gives the following numbers:
M1 sheet resistance: 0.092 ohms/sq.
M1 capacitance: 0.199 ff/u (minimum width metal)
M2 sheet resistance: 0.075 ohms/sq.
M2 capacitance: 0.207 ff/u
M3 sheet resistance: 0.075 ohms/sq.
M3 capacitance: 0.204 ff/u
From the looks of the tables, these are based on some 3d simulations of the
metal structures under various configurations of metal pitch and layer
arrangements. NEC boiled them down to one number for us...
So... the RC delay of a wire, using a lumped capacitance model is:
((0.092/0.68) * 25.4) * (0.199 * 25.4) = 0.0174 ps/mil or ~30
ps/mm
^ ^ ^ ^ ^
| | | | |
ohms width u/mil ff u/mil
Hardly anything to worry about... ( ~400ps from corner to corner on the die)
If you want to be conservative figure in 0.2 - 0.5 ns for long routes.
The capacitive loading delay factor is:
C = (0.207 * 25.4) = 0.0053 pf/mil
For a 1x drive flip-flop this adds: 0.0053 * 4.58 = ~0.03ns/mil (1.2 ns/mm)
" " 2x " " " " " : 0.0053 * 2.34 = ~0.015ns/mil (0.6 ns/mm)
" " 4x " buffer " " : 0.0053 * 0.89 = ~0.005ns/mil (0.2 ns/mm)
Here's some rough estimates for different routing delays:
4x buffer: 14mm * 0.2ns + 0.5ns =~ 3.3ns (corner to corner)
4x buffer: 8mm * 0.2ns + 0.3ns =~ 1.9ns (corner to center)
4x buffer: 4mm * 0.2ns + 0.2ns =~ 1.0ns (> half of one side)
2x flop: 4mm * 0.6ns + 0.2ns =~ 2.6ns (same as above)
2x flop: 1mm * 0.6ns =~ 0.6ns
You can choose which example is best for your application, or make up your
own...