pi.tst
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//****************************************************************************
//
// File: pi.tst
// Test file for Peripheral Interface (PI)
//
// $Revision: 1.1.1.1 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//****************************************************************************
//****************************************************************************
// Configure RDRAM
t 0000 00000000 00000000 00000000 00000000
// Config PI Domain 1: lat, pwd, pgs, rls
t 0001 00000080 00000020 00000002 00000003
// Config PI Domain 2: lat, pwd, pgs, rls
t 0002 00000080 00000020 00000002 00000003
// Init RDRAM with pattern data (rdram_addr, nwords, pattern_key)
t 0013 00000000 00000080 81234567 00000000
//****************************************************************************
// W/R PI DRAM Address Reg: address, data, expected_data -> SHOULD PASS
t 0103 04600000 00000001 00000000 00000000
t 0103 04600000 00000012 00000012 00000000
t 0103 04600000 00001200 00001200 00000000
t 0103 04600000 00120000 00120000 00000000
t 0103 04600000 12000000 00000000 00000000
//****************************************************************************
// W/R PI Cartridge Address Reg: address, data, expected_data -> SHOULD PASS
t 0103 04600004 00000001 00000000 00000000
t 0103 04600004 00000012 00000012 00000000
t 0103 04600004 00001200 00001200 00000000
t 0103 04600004 00120000 00120000 00000000
t 0103 04600004 12000000 12000000 00000000
//****************************************************************************
// Read from PI ROM address: address, data -> SHOULD PASS
t 0101 08000000 01000302 00000000 00000000
t 0101 08000004 05040706 00000000 00000000
t 0101 08000008 09080b0a 00000000 00000000
t 0101 0800000c 0d0c0f0e 00000000 00000000
t 0101 08000020 21202322 00000000 00000000
t 0101 10000000 00000001 00000000 00000000
t 0101 10000004 00020003 00000000 00000000
t 0101 10000008 00040005 00000000 00000000
t 0101 1000000c 00060007 00000000 00000000
t 0101 10000020 00100011 00000000 00000000
//****************************************************************************
// W/R PI Cartridge: address, data, expected_data -> SHOULD PASS
t 0103 09000000 11223344 11223344 00000000
t 0103 09000004 55667788 55667788 00000000
t 0103 09000008 99aabbcc 99aabbcc 00000000
t 0103 097cff00 ddeeff00 ddeeff00 00000000
t 0103 097cff0c 12344321 12344321 00000000
t 0103 097cfffc 1020efb9 1020efb9 00000000
//****************************************************************************
// Test PI DMA: direction (1=from_RAM, 2=to_RAM),
// pi_address, ram_address, size
//****************************************************************************
// DMA: Minimal length (2 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000000 00000002
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000000 00000002 00000000
//****************************************************************************
// Now, test for DMA busy bit -> SHOULD PASS
t 0026 00000001 00000000 00000000 00000000
t 0104 04600010 00000001 00000001 00000000
// Now, test for interrupt bit
t 0104 04600010 00000008 00000000 00000000
// Here, we clear interrupt by writing to bit 1 of status register
t 0102 04600010 00000002 00000000 00000000
// Now, test for interrupt bit
t 0104 04600010 00000008 00000001 00000000
//****************************************************************************
// DMA: length (4 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000008 00000004
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000000 00000008 00000004 00000000
//****************************************************************************
// DMA: length (6 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000010 00000006
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000010 00000006 00000000
//****************************************************************************
// DMA: length (8 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000020 00000008
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000020 00000008 00000000
//****************************************************************************
// DMA: length (32 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000040 00000020
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000040 00000020 00000000
//****************************************************************************
// DMA: Buffer-size length (128 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000080 00000080
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000000 00000080 00000080 00000000
//****************************************************************************
// Reset PI controller to turn off error bit
// First, read status to verify that error bit is set;
// then write to status register (bit 0) to reset PI controller
// and check for error bit to be cleared
t 0104 04600010 00000004 00000000 00000000
t 0102 04600010 00000001 00000000 00000000
t 0104 04600010 00000004 00000001 00000000
//****************************************************************************
// DMA: More-than-buffer-size length (132 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000040 00000080 00000084
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000040 00000080 00000084 00000000
//****************************************************************************
// DMA: Across DMA page boundary xfer -> SHOULD PASS
t 0023 00000002 08000070 00000100 00000020
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000070 00000100 00000020 00000000
//****************************************************************************
// DMA: Across RDRAM page boundary xfer -> SHOULD PASS
t 0023 00000002 08000000 000007E0 00000020
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 08000000 000007E0 00000020 00000000
//****************************************************************************
// DMA: RDRAM -> ROM: across RDRAM page boundary -> SHOULD PASS
t 0023 00000001 09000010 000007E0 00000020
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 09000010 000007E0 00000020 00000000
//****************************************************************************
// DMA: RDRAM -> ROM: across ROM page boundary -> SHOULD PASS
t 0023 00000001 09050008 00000000 00000024
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 09050008 00000000 00000024 00000000
//****************************************************************************
// DMA: RDRAM -> ROM: across ROM boundary -> SHOULD PASS
// Rom size = 8MB = 0x7d0000
t 0023 00000001 097cffe0 00000000 00000024
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 097cffe0 00000000 00000024 00000000
//****************************************************************************
// Issue DMA (RDRAM->ROM), issue IO Read to cause error bit set -> IO FAIL
t 0023 00000001 097b00f0 00000010 00000020
// Do IO read -> this should cause error bit to set
// ***** ERROR READ FAILED *******
t 0101 10000020 00100011 00000000 00000001
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 097b00f0 00000010 00000020 00000000
//****************************************************************************
// Now, test for error bit and reset it if necessary
t 0026 00000004 00000001 00000000 00000000
t 0104 04600010 00000004 00000001 00000000
//****************************************************************************
// Issue 2 DMAs: RDRAM -> ROM: 16 bytes -> 1st DMA SHOULD PASS, 2nd FAIL
t 0023 00000001 09000000 00000000 00000010
t 0023 00000002 08000000 00000100 00000010
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 09000000 00000000 00000010 00000000
t 0105 08000000 00000100 00000010 00000001
//****************************************************************************
// Do IO read, DMA, IO read, DMA -> 2nd IO read & 2nd DMA FAIL
t 0101 10000020 00100011 00000000 00000000
t 0023 00000001 09000010 00000000 00000010
// ****** ERROR READ FAILED ********
t 0101 10000030 00200021 00000000 00000001
t 0023 00000002 08000000 00000110 00000010
// Now, test for DMA busy and IO busy bits
t 0104 04600010 00000003 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 09000010 00000000 00000010 00000000
t 0105 08000000 00000110 00000010 00000001
//****************************************************************************
// Reset PI controller to turn off error bit
// First, read status to verify that error bit is set;
// then write to status register (bit 0) to reset PI controller
// and check for error bit to be cleared
t 0104 04600010 00000004 00000000 00000000
t 0102 04600010 00000001 00000000 00000000
t 0104 04600010 00000004 00000001 00000000
//****************************************************************************
// DMA 8B+ from ROM -> DRAM npages -> SHOULD PASS
// (dma_type, pi_address, dram_address, npages)
t 0027 00000002 08000000 00000000 00000005
// Now, test for DMA busy bit to clear
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000000 00000008 00000000
t 0105 08000000 00000800 0000000a 00000000
t 0105 08000000 00001000 0000000c 00000000
t 0105 08000000 00001800 0000000e 00000000
t 0105 08000000 00002000 00000010 00000000
//****************************************************************************
// Config PI Domain 1: lat, pwd, pgs, rls NOT A TEST
t 0001 00000080 00000020 00000006 00000003
// Config PI Domain 2: lat, pwd, pgs, rls
t 0002 00000080 00000020 00000006 00000003
//****************************************************************************
// DMA long from ROM -> DRAM
// DMA: length (264 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000000 00000040 00000108
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000000 00000040 00000108 00000000
//****************************************************************************
// DMA long from ROM -> DRAM
// DMA: length (264 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000004 00000040 00000108
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000004 00000040 00000108 00000000
//****************************************************************************
// DMA long from ROM -> DRAM
// DMA: length (264 bytes) xfer -> SHOULD PASS
t 0023 00000002 08000078 00000040 00000108
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 08000078 00000040 00000108 00000000
//****************************************************************************
// DMA long from ROM -> DRAM
// DMA: length (264 bytes) xfer -> SHOULD PASS
t 0023 00000002 0800007C 00000040 00000108
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 0800007C 00000040 00000108 00000000
//****************************************************************************
// DMA long from ROM -> DRAM
// DMA: length (268 bytes) xfer -> SHOULD PASS
t 0023 00000002 080002F4 00000040 0000010C
// Now, test for DMA busy bits
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 080002F4 00000040 0000010C 00000000
//****************************************************************************
// Config PI Domain 1: lat, pwd, pgs, rls NOT A TEST
t 0001 00000080 00000020 00000002 00000003
// Config PI Domain 2: lat, pwd, pgs, rls
t 0002 00000080 00000020 00000002 00000003
//****************************************************************************
// DMA long from DRAM -> ROM
// DMA: RDRAM -> ROM: across ROM boundary -> SHOULD PASS
// Rom size = 8MB = 0x7d0000
t 0023 00000001 097FFFF4 00000000 00000008
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 097FFFF4 00000000 00000008 00000000
//****************************************************************************
// DMA long from DRAM -> ROM
// DMA: RDRAM -> ROM: across ROM boundary -> SHOULD PASS
// Rom size = 8MB = 0x7d0000
t 0023 00000001 097FFF74 00000000 0000008C
// Now, test for DMA busy bit
t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
t 0105 097FFF74 00000000 0000008C 00000000
//****************************************************************************
// Config PI Domain 1: lat, pwd, pgs, rls NOT A TEST
t 0001 00000080 00000020 0000000f 00000003
// Config PI Domain 2: lat, pwd, pgs, rls
t 0002 00000080 00000020 0000000f 00000003
//****************************************************************************
// DMA >max page size from DRAM -> ROM
// COMMENTED OUT BECAUSE IT TAKES TOO LONG
// t 0023 00000001 0901FFF4 00020000 00020010
// Now, test for DMA busy bit
// t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
// t 0105 0901FFF4 00020000 00020010 00000000
//****************************************************************************
// DMA >max page size from ROM -> DRAM
// t 0023 00000002 0901FFF4 001017F8 00020010
// Now, test for DMA busy bit
// t 0104 04600010 00000001 00000001 00000000
// Now we compare data (pi_address, dram_address, nbytes)
// t 0105 0901FFF4 001017F8 00020010 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q