.TH osWritebackDCache 3P local "Silicon Graphics, Inc."
.SH NAME
.upperok
osWritebackDCache, osWritebackDCacheAll \- write back CPU data cache lines to physical memory
.SH SYNOPSIS
.nf
\f3
.Op c
#include <ultra64.h>
.sp .8v
void osWritebackDCache(void \(**vaddr, s32 nbytes);
.sp .8v
void osWritebackDCacheAll(void);
.Op
\f1
.fi
.SH DESCRIPTION
The MIPS R4300 CPU implements a 8 kilobyte direct mapped data cache
with a line size of 16 bytes.
The cache implements a "write back" replacement policy which means
that data stores are held in the cache until the entire cache line is
written back,
usually due to a cache miss that requires the same cache line.
The cache is not coherent with respect to physical memory and
thus cache lines must be explicitly written back when it is desired that
the DRAM be updated with the more recent data in the data cache.
The
.I osWritebackDCache
call writes back all data cache lines that contain the region
.IR  "[vaddr, vaddr + nbytes)" .
The given address
.I vaddr
must be a CPU virtual address,
either direct mapped or mapped via the CPU TLB.
If
.I vaddr
is not aligned to the a cache line boundary,
and
.I nbytes
is not a multiple of the cache line size,
a slightly larger region may be written back to memory.
.PP
The
.I osWritebackDCacheAll
routine writes back all cached locations to physical memory.
.PP
This routine is most commonly used in the situation where a direct memory
access (DMA) device needs to read physical memory locations,
but current contents associated with these memory locations are
currently stored in the cache.
In this case, the memory is out of date with respect to the cache,
and the cache lines associated with these locations must be written back
prior to performing the DMA operation.
.SH "SEE ALSO"
.IR osMapTLB (3P),
.IR osInvalDCache (3P),
.IR osInvalICache (3P)