rdp_v.v
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// Verilog model created from schematic rdp_v.sch
// 2002/05/13 8:54:02 AM
// vericode v2.1
// Schematic 'rdp_v.sch'
module rdp_v;
wire [31:0] FILL_CLR;
wire [1:0] CYC_TYPE;
wire [25:0] Z_BASE;
wire [1:0] CLR_SZ;
wire [2:0] CLR_FMT;
wire [25:0] CLR_BASE;
wire [17:0] SPAN_Z;
wire [2:0] SPAN_A;
wire [7:0] SPAN_B;
wire [7:0] SPAN_G;
wire [17:0] MEM_Z;
wire [7:0] SPAN_R;
wire [2:0] MEM_A;
wire [11:0] EW_MS_LENGTH;
wire [7:0] MEM_B;
wire [19:0] EW_MS_ADDR;
wire [7:0] MEM_G;
wire [7:0] MEM_R;
wire [63:0] XBUS_DATA;
wire [63:0] COPY_LOAD;
wire [25:0] TEX_BASE;
wire [9:0] TEX_WIDTH;
wire [1:0] TEX_SIZE;
wire [2:0] TEX_FORMAT;
wire LOAD_TLUT_EN;
wire EW_MS_STSPAN;
wire CLOCK;
wire GCLOCK;
wire GCLOCK_ENABLE;
wire REL_SYNC_FULL;
wire COPY_LOAD_E;
wire STROBE_SYNC_FULL;
wire TC_LOAD;
wire EW_SCISSOR_LOAD;
wire REQUEST;
wire XBUS_DV;
wire RESET_L;
wire FLUSH;
wire EW_MS_NEWSPAN;
wire SPAN_CLR_WE;
wire EXIT;
wire SPAN_Z_WE;
wire CLR_RMW;
wire Z_RMW;
wire Z_EN;
wire CAPTURE;
ms_ck CLOCK_DRIVER (.CLOCK(CLOCK), .GCLOCK(GCLOCK), .GCLOCK_ENABLE(GCLOCK_ENABLE));
mspan MSPAN (.AT_COLOR_BASE(CLR_BASE[25:0]), .AT_COLOR_FORMAT(CLR_FMT[2:0]),
.AT_COLOR_RMW(CLR_RMW), .AT_COLOR_SIZE(CLR_SZ[1:0]), .AT_CYCLE_TYPE(CYC_TYPE[1:0]),
.AT_FILL_COLOR(FILL_CLR[31:0]), .AT_TEX_BASE(TEX_BASE[25:0]),
.AT_TEX_FORMAT(TEX_FORMAT[2:0]), .AT_TEX_SIZE(TEX_SIZE[1:0]),
.AT_TEX_WIDTH(TEX_WIDTH[9:0]), .AT_Z_BASE(Z_BASE[25:0]),
.AT_Z_ENABLE(Z_EN), .AT_Z_RMW(Z_RMW), .BL_A(SPAN_A[2:0]),
.BL_B(SPAN_B[7:0]), .BL_COLOR_WE(SPAN_CLR_WE), .BL_G(SPAN_G[7:0]),
.BL_MEM_A(MEM_A[2:0]), .BL_MEM_B(MEM_B[7:0]), .BL_MEM_G(MEM_G[7:0]),
.BL_MEM_R(MEM_R[7:0]), .BL_MEM_Z(MEM_Z[17:0]), .BL_R(SPAN_R[7:0]),
.BL_Z(SPAN_Z[17:0]), .BL_Z_WE(SPAN_Z_WE), .CAPTURE(CAPTURE),
.EW_CV_NEWSPAN(EW_MS_NEWSPAN), .EW_MS_ADDR(EW_MS_ADDR[19:0]),
.EW_MS_LENGTH(EW_MS_LENGTH[11:0]), .EW_SCISSOR_LOAD(EW_SCISSOR_LOAD),
.EXIT(EXIT), .GCLK(CLOCK), .GCLK_EN(GCLOCK_ENABLE), .MS_LOAD_TLUT(LOAD_TLUT_EN),
.REL_SYNC_FULL(REL_SYNC_FULL), .RESET(RESET_L), .STROBE_SYNC_FULL(STROBE_SYNC_FULL),
.TEX_BUS(COPY_LOAD[63:0]), .TEX_DATA_VALID(COPY_LOAD_E));
driver DRIVER (.CLK(CLOCK), .FLUSH(FLUSH), .GCLK_EN(GCLOCK_ENABLE),
.REQUEST(REQUEST), .RESET(RESET_L), .WR_FB(CAPTURE), .XBUS_CS_DATA(XBUS_DATA[63:0]),
.XBUS_CS_VALID(XBUS_DV), .ZERO());
rdp_ms RDP_MS (.AT_COLOR_BASE(CLR_BASE[25:0]), .AT_COLOR_FORMAT(CLR_FMT[2:0]),
.AT_COLOR_SIZE(CLR_SZ[1:0]), .AT_CYCLE_TYPE(CYC_TYPE[1:0]),
.AT_FILL_COLOR(FILL_CLR[31:0]), .AT_Z_BASE(Z_BASE[25:0]),
.AT_Z_ENABLE(Z_EN), .AT_Z_RMW(Z_RMW), .CLK(CLOCK), .COLOR_RMW(CLR_RMW),
.COPY_LOAD(COPY_LOAD[63:0]), .CS_XBUS_REQ(REQUEST), .EW_MS_ADDR(EW_MS_ADDR[19:0]),
.EW_MS_LENGTH(EW_MS_LENGTH[11:0]), .EW_MS_NEWSPAN(EW_MS_NEWSPAN),
.EW_MS_STARTSPAN(EW_MS_STSPAN), .EW_SCISSOR_LOAD(EW_SCISSOR_LOAD),
.FLUSH(FLUSH), .GCLK(GCLOCK), .GCLOCK_ENABLE(GCLOCK_ENABLE),
.LOAD_DV(COPY_LOAD_E), .LOAD_TLUT_EN(LOAD_TLUT_EN), .MEM_A(MEM_A[2:0]),
.MEM_B(MEM_B[7:0]), .MEM_G(MEM_G[7:0]), .MEM_R(MEM_R[7:0]),
.MEM_Z(MEM_Z[17:0]), .REL_SYNC_FULL(REL_SYNC_FULL), .RESET_L(RESET_L),
.SPAN_A(SPAN_A[2:0]), .SPAN_B(SPAN_B[7:0]), .SPAN_COLOR_WE(SPAN_CLR_WE),
.SPAN_DEPTH_WE(SPAN_Z_WE), .SPAN_G(SPAN_G[7:0]), .SPAN_R(SPAN_R[7:0]),
.SPAN_Z(SPAN_Z[17:0]), .STROBE_SYNC_FULL(STROBE_SYNC_FULL),
.TC_LOAD(TC_LOAD), .TEX_BASE(TEX_BASE[25:0]), .TEX_FORMAT(TEX_FORMAT[2:0]),
.TEX_SIZE(TEX_SIZE[1:0]), .TEX_WIDTH(TEX_WIDTH[9:0]),
.XBUS_CS_DATA(XBUS_DATA[63:0]), .XBUS_CS_VALID(XBUS_DV));
endmodule