Makefile
921 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
#!smake
#
#
#
# $Revision: 1.1.1.1 $
#
#
# Tools
#
PRDEPTH = ../../../..
ECS2VL = $(PRDEPTH)/rdpsim/tools/ecs2vl
ASYIN = /hosts/venice/ecad/ecs/ecs_2.4/bin/asyin
RMVCOM = $(PRDEPTH)/rdpsim/tools/remove_comments
ECSGEN = $(PRDEPTH)/rdpsim/tools/ecs_gen
#
# SGI Common Defs
#
include $(PRDEPTH)/PRdefs
#
# Sources
#
HW = $(PRDEPTH)/hw/chip/rcp
VERILOG = $(HW)/ew/src/ew.v
VERILOGDIRS = $(VERILOG:H)
SYMNAMES = $(VERILOG:T)
SYMBOLS = $(SYMNAMES:.v=.sym)
#
# Set path to find verilog sources
#
.PATH: $(VERILOGDIRS)
#
# Targets
#
GCINCS =
LDIRT = ew_test.1 *.asy $(SYMBOLS)
TARGETS = ew_test
default install: $(TARGETS)
#
# SGI Common Rules
#
include $(COMMONRULES)
#
# Make Blender Netlist
#
ew_test: ew_test.sch driver.sym $(SYMBOLS)
$(ECS2VL) $* $*.1
#
# Suffix Rules
#
.SUFFIXES : .v .sym
.v.sym:
$(RMVCOM) < $*.v | $(ECSGEN)
echo "TEXT 0 0 Left 2 $(*:T)" >> $(*:T).asy
$(ASYIN) $(*:T).asy