rsp.v
3.61 KB
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module rsp (.clk(clock), reset_l, iddq_test,
sp_cbus_read_enable, sp_cbus_write_enable, mem_cbus_write_enable,
cmd_cbus_read_enable, cmd_cbus_write_enable, cbus_select,
cbus_command, dma_start, dma_last, sp_dma_grant, sp_read_grant,
cmd_dma_grant, cmd_read_grant, sp_dbus_read_enable,
sp_dbus_write_enable, cbuf_ready,
cmd_busy, pipe_busy, tmem_busy, frozen,
sp_dma_request, sp_read_request, mem_read_request, cmd_dma_request,
cmd_read_request, cbuf_write, flush, freeze, unfreeze, sp_interrupt,
xbus_data, cbus_data, dbus_data);
`include "sp.vh"
input clock; // system clock
input reset_l; // system reset_l
input iddq_test;
input sp_cbus_read_enable; // enable cbus read mux
input sp_cbus_write_enable; // enable cbus tristate drivers
input mem_cbus_write_enable; // enable cbus tristate drivers
input cmd_cbus_read_enable; // enable cbus read mux
input cmd_cbus_write_enable; // enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select; // cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command; // cbus transaction type
input dma_start; // dbus DMA data start
input dma_last; // dbus DMA data end
input sp_dma_grant; // SP DMA request granted
input sp_read_grant; // SP read request granted
input cmd_dma_grant; // DP DMA request granted
input cmd_read_grant; // DP read request granted
input sp_dbus_read_enable; // enable dbus read register
input sp_dbus_write_enable; // enable dbus tristate drivers
input cbuf_ready; // cbuf ready for write data
input cmd_busy; // DP CMDBUF is not empty
input pipe_busy; // DP pipeline is active
input tmem_busy; // DP TMEM is loading
input frozen;
output sp_dma_request; // SP DMA request
output sp_read_request; // SP read request
output mem_read_request; // DMEM/IMEM read request
output cmd_dma_request; // DP DMA request
output cmd_read_request; // DP read request
output cbuf_write; // DP command buffer write
output flush; // DP control
output freeze; // DP control
output unfreeze; // DP control
output sp_interrupt; // sp generated interrupt
output [XBUS_DATA_SIZE-1:0] xbus_data; // SP-DP private bus
inout [CBUS_DATA_SIZE-1:0] cbus_data; // IO bus
inout [DBUS_DATA_SIZE-1:0] dbus_data; // DMA bus
wire [SP_REG_DATA_SIZE-1:0] cp0_data; // DMA register write data
wire cp0_cmd_select; // DMA register address
wire [SP_REG_ADDRESS_SIZE-1:0] cp0_address; // DMA register address
wire cp0_write; // register write
wire cp0_enable; // enable read data on cp0_data
wire imem_select; // DMEM read/write select
wire [SP_MEM_ADDRESS_SIZE-1:0] mem_address; // SP DMA memory address
wire mem_read; // enable mem write
wire mem_write; // enable mem read
wire [SP_MEM_MASK_SIZE-1:0] mem_mask; // read/write byte mask
wire xbus_dmem_dma; // CMD DMEM/DRAM select
wire halt; // halt RSP
wire single_step;
wire dma_busy; // SP DMA busy
wire set_broke; // SP break flag
wire cmd_ready; // SP DMEM read ready
wire cmd_read; // SP DMEM read request
wire [SP_MEM_ADDRESS_SIZE-1:0] cmd_address; // DP DMEM read address
wire pc_write; // SP PC write enable
wire [SP_PC_SIZE-1:0] pc_data; // SP PC write data
reg bist_done;
reg [SP_BIST_FAIL_SIZE-1:0] bist_fail;
wire bist_go;
wire bit_check;
always @(negedge reset_l) begin
bist_done = LOW;
bist_fail = 0;
end
assign set_broke = LOW;
assign freeze = LOW;
assign unfreeze = LOW;
endmodule