test003.v
1.45 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
//
// test003 First write, and then read all pages of all banks
// of both rams
//
`define DW_SIZE 8
task test003;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
reg [EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;
integer bank, ram, dw;
begin
for (ram = 0; ram < `NUM_RAMS; ram = ram + 1)
begin
for (bank = 0; bank < `NUM_BANKS; bank = bank + 1)
begin
address = (ram * (`NUM_BANKS * `BANK_SIZE)) + (bank * `BANK_SIZE);
for (dw = 0; dw < (`NUM_PAGES * `PAGE_SIZE) / `DW_SIZE; dw = dw + 1)
begin
expected_d_data = {2{address}};
expected_e_data = address[10:3];
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address,
BUS_DEVICE_MI, -2, 8);
dbus_put_data(expected_d_data, expected_e_data, -2);
address = address + `DW_SIZE;
end
end
end
for (ram = 0; ram < `NUM_RAMS; ram = ram + 1)
begin
for (bank = 0; bank < `NUM_BANKS; bank = bank + 1)
begin
address = (ram * (`NUM_BANKS * `BANK_SIZE)) + (bank * `BANK_SIZE);
for (dw = 0; dw < (`NUM_PAGES * `PAGE_SIZE) / `DW_SIZE; dw = dw + 1)
begin
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address,
BUS_DEVICE_MI, 3, 8);
dbus_get_data(actual_d_data, actual_e_data, 3);
expected_d_data = {2{address}};
expected_e_data = address[10:3];
check_data("test003", expected_d_data, actual_d_data,
expected_e_data, actual_e_data);
address = address + `DW_SIZE;
end
end
end
end
endtask