test010.v
2.19 KB
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//
// test010 Read/write hazard test
//
`define MAX_TRANSFER 'h10
task test010;
begin
fork
test010_cmd;
test010_putdata;
test010_getdata;
join
end
endtask
task test010_cmd;
reg [CBUS_DATA_SIZE-1:0] address;
integer i;
begin
address = 0;
for (i = 0; i < 2; i = i + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, 0,
BUS_DEVICE_MI, -1, `MAX_TRANSFER * 8);
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, 0,
BUS_DEVICE_MI, 0, `MAX_TRANSFER * 8);
end
end
endtask
task test010_putdata;
integer i, j;
begin
// put the data for word 0 out on the bus ahead of the start
dbus_data_out <= 64'h00000000_00000000;
ebus_data_out <= 8'h00;
while (!dma_start)
@(posedge clock);
for (j = 1; j < `MAX_TRANSFER; j = j + 1)
begin
dbus_data_out <= 64'h00000000_00000000;
ebus_data_out <= 8'h00;
@(posedge clock);
end
// again, put the data for word 0 out on the bus (for next write)
dbus_data_out <= 64'hffffffff_ffffffff;
ebus_data_out <= 8'hff;
// skip the dma_start for the following read
while (!dma_start)
@(posedge clock);
@(posedge clock);
while (!dma_start)
@(posedge clock);
for (j = 1; j < `MAX_TRANSFER; j = j + 1)
begin
dbus_data_out <= 64'hffffffff_ffffffff;
ebus_data_out <= 8'hff;
@(posedge clock);
end
end
endtask
task test010_getdata;
integer i, j;
begin
// skip the dma_start for the first write
while (!dma_start)
@(posedge clock);
@(posedge clock);
while (!dma_start)
@(posedge clock);
repeat(3)
@(posedge clock);
for (j = 0; j < `MAX_TRANSFER; j = j + 1)
begin
check_data("test010", 64'h00000000_00000000, dbus_data_reg,
8'h00, ebus_data_reg);
@(posedge clock);
end
// skip the dma_start for the second write
while (!dma_start)
@(posedge clock);
while (!dma_start)
@(posedge clock);
repeat(3)
@(posedge clock);
for (j = 0; j < `MAX_TRANSFER; j = j + 1)
begin
check_data("test010", 64'hffffffff_ffffffff, dbus_data_reg,
8'hff, ebus_data_reg);
@(posedge clock);
end
end
endtask