//
// test014	Perform writes, then reads using previously tested modes.
//		Perform the DMA by concurrent cmd and data threads.
//		Uses a write delay of -1 and a read delay of 3.
//

`define	MAX_TRANSFER	'h10

task test014;
  begin 
    fork
      test014_check;
      test014_cmd;
      test014_data;
    join
  end
endtask

task test014_check;
  begin
    check_unmasked("test014");
    check_nosubblock("test014");
    check_unmasked("test014");
    check_nosubblock("test014");
    check_masked("test014");
    check_nosubblock("test014");
    check_masked("test014");
    check_nosubblock("test014");
  end
endtask

task test014_cmd;
  begin
    test014_cmd_unmasked(`DMA_UP);
    test014_cmd_nosubblock(`DMA_UP);
    test014_cmd_unmasked(`DMA_DOWN);
    test014_cmd_nosubblock(`DMA_DOWN);
    test014_cmd_masked(`DMA_UP);
    test014_cmd_nosubblock(`DMA_UP);
    test014_cmd_masked(`DMA_DOWN);
    test014_cmd_nosubblock(`DMA_DOWN);
  end
endtask

task test014_cmd_unmasked;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin 
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      cbus_dma_write(`DMA_UNMASKED, down, address, BUS_DEVICE_MI, -1, i*8);
      if (down)
	address = address - (i*8);
      else
	address = address + (i*8);
    end
  end
endtask

task test014_cmd_nosubblock;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      cbus_dma_read(`DMA_NOSUBBLOCK, down, address, BUS_DEVICE_MI, 3, i*8);
      if (down)
	address = address - (i*8);
      else
	address = address + (i*8);
    end
  end
endtask

task test014_cmd_masked;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin 
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
    begin
      cbus_dma_write(`DMA_MASKED, down, address, BUS_DEVICE_MI, -1, i*8);
      if (down)
        address = address - (i*8);
      else
        address = address + (i*8);
    end
  end
endtask

task test014_cmd_subblock;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i;

  begin
    address = 0;

    for (i = 0; i < 2; i = i + 1)
    begin
      cbus_dma_read(`DMA_SUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 2*8);
      address = address + 8;
    end
    for (i = 0; i < 4; i = i + 1)
    begin
      cbus_dma_read(`DMA_SUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 4*8);
      address = address + 8;
    end
  end
endtask
task test014_data;
  begin
    test014_data_unmasked(`DMA_UP);
    test014_data_nosubblock(`DMA_UP);
    test014_data_unmasked(`DMA_DOWN);
    test014_data_nosubblock(`DMA_DOWN);
    test014_data_masked(`DMA_UP);
    test014_data_nosubblock(`DMA_UP);
    test014_data_masked(`DMA_DOWN);
    test014_data_nosubblock(`DMA_DOWN);
  end
endtask

task test014_data_unmasked;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      dbus_data_out <= {2{address}};
      ebus_data_out <= address[10:3];

      while (!dma_start)
	@(posedge clock);

      if (down)
	address = address - 8;
      else
	address = address + 8;

      if (i == 1)
	@(posedge clock);
      else
	for (j = 1; j < i; j = j + 1)
	begin
	  dbus_data_out <= {2{address}};
	  ebus_data_out <= address[10:3];
	  @(posedge clock);
	  if (down)
	    address = address - 8;
	  else
	    address = address + 8;
	end
    end
  end
endtask

task test014_data_nosubblock;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
    begin
      while (!dma_start)
	@(posedge clock);

      for (j = 0; j < i; j = j + 1)
      begin
	check_data("test014", {2{address}}, dbus_data_reg,
			      address[10:3], ebus_data_reg);

	@(posedge clock);
	if (down)
	  address = address - 8;
	else
	  address = address + 8;
      end
    end
  end
endtask

task test014_data_masked;
  input		down;
  reg		[CBUS_DATA_SIZE-1:0] address;
  integer	i, j;

  begin
    address = 0;
    if (down)
    begin
      for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
      begin
	for (j = 0; j < i; j = j + 1)
	begin
	  address = address + 8;
	end
      end
      address = address - 8;
    end

    for (i = 1; i <= `MAX_MASKEDTRANSFER; i = i + 1)
    begin
      dbus_data_out <= {2{address}};
      ebus_data_out <= address[10:3];

      while (!dma_start)
	@(posedge clock);

      dbus_data_out <= 64'hffffffff_ffffffff;
      ebus_data_out <= 8'hff;
      @(posedge clock);

      if (down)
	address = address - 8;
      else
	address = address + 8;

      if (i == 1)
	@(posedge clock);
      else
	for (j = 1; j < i; j = j + 1)
	begin
	  dbus_data_out <= {2{address}};
	  ebus_data_out <= address[10:3];
	  @(posedge clock);
	  if (down)
	    address = address - 8;
	  else
	    address = address + 8;
	end
    end
  end
endtask