/************************************************************************
  WHAT: RSP DUAL-ISSUE VERIFICATION TEST PROGRAM GENERATOR
  SCCS: @(#)main.c	1.2 21 Sep 1994
  PTLS: $Id: main.c,v 1.1.1.1 2002/05/02 03:29:13 blythe Exp $
  ENGR:	Project Reality - Evan Y. Wang
  (CR):	1994 Silicon Graphics, Inc.
 ************************************************************************/
#include <stdio.h>
#include <math.h>
#include "software.h"
#include "digen.h"

FILE	*fhTFile;
char	cTFName[20];

DATA	VReg[32][4];
DATA	Reg[32];
u32	IP, Dadr;
u16	VCR[3];		/* VCO = 0, VCC = 1, VCE = 2 */


/************************************************************************
  Header(..) - print common test program header/comment.
 ************************************************************************/
PRIVATE void Header(outp, name)
    FILE *outp;
    char *name;
{
    int i;

    fprintf(stderr,"Generating %s...", cTFName);
    fprintf(outp,"/****************************************************************\n");
    fprintf(outp,"  RSP DUAL ISSUE: %s\n", name);
    fprintf(outp," ****************************************************************/\n\n");
    fprintf(outp,".base 0x%8.8lX\n\n",IMEM_BASE);

    /************************************************************
      SIMPLE INITIALIZATION
     ************************************************************/
    IP = 0;
    Dadr = DMEM_BASE;

    for (i=0; i<32; i++) {
	VReg[i][0].w = (u32) (rand()<<16 | rand());
	VReg[i][1].w = (u32) (rand()<<16 | rand());
	VReg[i][2].w = (u32) (rand()<<16 | rand());
	VReg[i][3].w = (u32) (rand()<<16 | rand());
	Reg[i].w = (u32) (rand()<<16 | rand());
    }
    Reg[0].w = 0;

}   /* Header */

/************************************************************************
  Tail(..) - print common test end statements.
 ************************************************************************/
PRIVATE void Tail(outp)
    FILE *outp;
{
    int i;
  
    fpORI(outp,1,0x0000FEED);
    for (i=0; i<32; i++) {
      fprintf(outp,"\tsw\t$%d, 0x%x($0);\n", i, 0xf80+(i*4));
    }
    fprintf(outp,"Fail:\tbreak;\n");
    fprintf(stderr,"done\n");
}   /* Tail */

/************************************************************************
  NORMAL DUAL-ISSUE TEST: EVEN AND ODD ALIGNMENT

  Alternating ADD and VADD instructions with no register hazards, resulting
  in maximal 2-group issuing.
 ************************************************************************/
void GenNorm(outp, align, type)
    FILE *outp;
    int  align;		/* starting alignment even = 0; odd = 1; */
    int  type;
{
    int i, j, k, m;
    u32 tmp;
    u32 tda[4];

    Header(outp,"Normal");

    /************************************************************
      Initialize VU Control Registers and Vector Register File
     ************************************************************/
    fpLIREG(outp,R1,DMEM_BASE);
    fpCTC2(outp,R0,VCO);
    fpCTC2(outp,R0,VCC);
    fpDATASEG(outp);
    tda[0] = 0x00010203;
    tda[1] = 0x04050607;
    tda[2] = 0x08090A0B;
    tda[3] = 0x0C0D0E0F;
    for (i=0; i<32; i++) { /* VuRFinit */
	fpLDVREG(outp,Vi,i*0x10,R1,tda[0],tda[1],tda[2],tda[3]);
	tda[0] += 0x00100010;	tda[1] += 0x00100010;
	tda[2] += 0x00100010;	tda[3] += 0x00100010;
    } /* VuRFinit */
    Dadr += i*0x10;

    /************************************************************
      Initialize SU Register File
     ************************************************************/
    tmp = 0x00010203;
    for (i=0; i<32; i++) { /* SuRFinit */
	fpLIREG(outp,Ri,tmp);
	tmp += 0x00030303;
    } /* SuRFinit */

    /************************************************************
      Align Instruction to "align"
     ************************************************************/
    if ((IP&1 && !align) || (!(IP&1) && align))	fpNOP(outp);

    /************************************************************
      Test Body
     ************************************************************/
    fpCOMMENT(outp,"TEST BODY");
    if (type == 0) {
	for (i=0; i<32; i++) { /* TestBody 1 */
	    j = (i+1)&0x1F;
	    k = (i+2)&0x1F;
	    fpADD( outp,Ri,Rj,Rk);
	    fpVADD(outp,Vi,Vj,Vk);
	} /* TestBody 1 */
    } else { /* TestBody 2 */
	for (i=0; i<32; i+=2) { /* TestBody 1 */
	    j = (i+1)&0x1F;
	    k = (i+2)&0x1F;
	    m = (i+3)&0x1F;
	    fpADD( outp,Ri,Rj,Rk);
	    fpADD( outp,Rj,Rk,Rm);
	    fpVADD(outp,Vi,Vj,Vk);
	    fpVADD(outp,Vj,Vk,Vm);
	} /* TestBody 1 */
    } /* TestBody 2 */

    /************************************************************
      Check Result
     ************************************************************/
    fpCOMMENT(outp,"CHECK RESULT");
    for (i=0; i<32; i++) { /* CheckSRF */
	fpLIREG(outp,R5,Reg[Ri].w);	/* arb'ly choose reg $5	*/
	fpBNE(outp,R5,Ri);	fpNOP(outp);
    } /* CheckSRF */

    fpLIREG(outp,R1,Dadr);
    fpLIREG(outp,R2,0xFF);
    for (i=0; i<32; i++) { /* CheckVRF */
	fpOR(outp,R3,R0,R0);		/* zero VU VCC reg	*/
	fpCTC2(outp,R3,VCC);	fpNOP(outp);
	fpLDVREG(outp,V5,i*0x10,R1,
		 VReg[Vi][0].w,VReg[Vi][1].w,VReg[Vi][2].w,VReg[Vi][3].w);
	fpVEQ(outp,V5,V5,Vi);	fpNOP(outp);
	fpCFC2(outp,R3,VCC);	fpNOP(outp);
	fpBNE(outp,R3,R2);	fpNOP(outp);
    } /* CheckVRF */

    Tail(outp);

} /* GenNorm */

/************************************************************************
  REGISTER HAZARD TEST: variable NOP separation.
 ************************************************************************/
void GenRegHz(outp,space)
    FILE *outp;
    int  space;
{
    int i, j, k, m;
    u32 tmp;

    Header(outp,"Register Hazard");

    /************************************************************
      Initialize SU Register File
     ************************************************************/
    tmp = 0x00010203;
    for (i=0; i<32; i++) { /* SuRFinit */
	fpLIREG(outp,Ri,tmp);
	tmp += 0x00030303;
    } /* SuRFinit */

    /************************************************************
      Initialize VU Register File
     ************************************************************/
    fpLIREG(outp,R1,DMEM_BASE);
    fpCTC2(outp,R0,VCO);
    fpCTC2(outp,R0,VCC);
    fpDATASEG(outp);
    fpLDVREG(outp,V0,0, R1,0x01010101,0x01010101,0x01010101,0x01010101);
    fpLDVREG(outp,V1,16,R1,0x02020202,0x02020202,0x02020202,0x02020202);
    Dadr += 0x20;
    for (i=2; i<32; i++) { fpVNXOR(outp,Vi,V0,V0); }

    /************************************************************
      Initialize SU Register File
     ************************************************************/
    tmp = 0x00010203;
    for (i=0; i<32; i++) { /* SuRFinit */
	fpLIREG(outp,Ri,tmp);
	tmp += 0x00030303;
    } /* SuRFinit */

    /************************************************************
      Test Body
     ************************************************************/
    fpCOMMENT(outp,"TEST BODY");
    for (i=2; i<34; i++) { /* TestBody */
	j = (i  )&0x1F;
	k = (i-1)&0x1F;
	for (m=0; m<space; m++)	fpNOP(outp);
	fpVADD(outp,Vj,V0,Vk);
    } /* TestBody */

    /************************************************************
      Check Result
     ************************************************************/
    fpCOMMENT(outp,"CHECK RESULT");
    fpLIREG(outp,1,Dadr);
    fpLIREG(outp,2,0xFF);	/* VCC */
    for (i=1; i<32; i++) { /* CheckVRF */
	fpXOR(outp,R3,R3,R3);
	fpLDVREG(outp,V0,(i-1)*0x10,R1,
		 VReg[Vi][0].w,VReg[Vi][1].w,VReg[Vi][2].w,VReg[Vi][3].w);
	fpVEQ(outp,V0,V0,Vi);	fpNOP(outp);
	fpCFC2(outp,R3,V1);	fpNOP(outp);
	fpBNE(outp,R3,R2);	fpNOP(outp);
    } /* CheckVRF */

    Tail(outp);

} /* GenRegHz */

/************************************************************************
  LOAD/STORE HAZARD TEST

  Algorithm:

    - Data segment is filled with known data.
    - VU load and store instructions are interweaved as:

        load  $v0  from 0x04000000  <-+
	load  $v1  from 0x04000010    | weave
        load  $v2  from 0x04000020  <-+
        store $v0  to   0x04000200
        load  $v3  from 0x04000030
	store $v1  to   0x04000210
	  :
        load  $v31  from 0x040001F0
	store $v29  to   0x040003E0
	store $v30  to   0x040003E0
        store $v31  to   0x040003F0
	
      with a programmable number of NOPs between each load/store instruction.

    - Finally, Memory locations 0x04000200-0x040003FF are checked against
      0x04000000-0x040001FF.

 ************************************************************************/
void GenLdSt(outp,space,weave)
    FILE *outp;
    int space;
    int weave;
{
    int i, j, k, l;
    u32 tmp;

    Header(outp,"Load/Store DMEM Contention");

    /************************************************************
      Initialize DMEM and VU Register File
     ************************************************************/
    fpCTC2(outp,R0,VCO);
    fpCTC2(outp,R0,VCC);
    fpDATASEG(outp);
    for (i=0; i<0x80; i++) { fpDATA(outp,0x01010101*i,Dadr); Dadr+=4; }
    fpLQV(outp,V0,0, R0);
    for (i=0; i<32; i++)   { fpVNXOR(outp,Vi,V0,V0); }

    /************************************************************
      Initialize SU Register File
     ************************************************************/
    tmp = 0x00010203;
    for (i=0; i<32; i++) { /* SuRFinit */
	fpLIREG(outp,Ri,tmp);
	tmp += 0x00030303;
    } /* SuRFinit */

    /************************************************************
      Test Body
     ************************************************************/
    fpCOMMENT(outp,"TEST BODY AND RESULT CHECK");
    fpLIREG(outp,1,Dadr);
    fpLIREG(outp,2,DMEM_BASE);

    for (i=0; i<weave; i++) {
	for (j=0; j<space; j++) fpNOP(outp);
	fpLQV(outp,Vi,i*0x10,R2);
    }
    for (k=0; i<32; i++, k++) {
	for (j=0; j<space; j++) fpNOP(outp);
	fpLQV(outp,i,i*0x10,R2);
	for (j=0; j<space; j++) fpNOP(outp);
	fpSQV(outp,Vk,k*0x10,R1);
    }
    for (; k<32; k++) {
	for (j=0; j<space; j++) fpNOP(outp);
	fpSQV(outp,Vk,k*0x10,R1);
    }

    /************************************************************
      Check Result
     ************************************************************/
    fpLIREG(outp,1,IMEM_BASE);







    fpLIREG(outp,2,DMEM_BASE);
    fpLIREG(outp,4,0xFF);
    for (i=0; i<32; i++) { /* CheckMem */
	fpXOR(outp,R3,R3,R3);
	fpLQV(outp,V1,i*0x10,R1);
	fpLQV(outp,V2,i*0x10,R2);
	fpVEQ(outp,V3,V1,V2);	fpNOP(outp);
	fpCFC2(outp,R3,V1);	fpNOP(outp);
	fpBNE(outp,R3,R4);	fpNOP(outp);
    } /* CheckMem */

    Tail(outp);

} /* GenLdSt */

/************************************************************************
  CONTROL REGISTER HAZARD TEST
 ************************************************************************/
void GenCtlHz(outp,space,align,type)
    FILE *outp;
    int  space;
    int  align;
    int  type;		/* type 0 = vadd; 1 = vaddc; 2 = "append" ctc2;	*/
{
    int g, h, i, j, k, m;
    u32 tmp;

    Header(outp,"Control Register Contention");

    /************************************************************
      Initialize SU Register File
     ************************************************************/
    tmp = 0x00010203;
    for (i=0; i<32; i++) { /* SuRFinit */
	fpLIREG(outp,Ri,tmp);
	tmp += 0x00030303;
    } /* SuRFinit */

    for (i=1; i<28; i++) { /* TestBody */
	/********************************************************
	  Initialize parameters.
	 ********************************************************/
	j = (i+1)&0x1F;
	k = (i+2)&0x1F;
	g = (i+3)&0x1F;
	h = (i+4)&0x1F;
	/********************************************************
	  Initialize a few important registers.
	 ********************************************************/
	fpLIREG(outp,Ri,Dadr);		/* data address	*/
	fpORI(outp,Rg,0xFF);		/* VCC check	*/
	VCR[VCO] = rand() & 0xFFFF;
	fpORI(outp,Rj,VCR[VCO]);
	VCR[VCO] = ~VCR[VCO] & 0xFFFF;
	fpORI(outp,Rk,VCR[VCO]);

	/* Predict result */
	fpLDVREG(outp,Vi,0x00,Ri,0x2A5A2A5A,0x2A5A2A5A,0x2A5A2A5A,0x2A5A2A5A);
	fpLDVREG(outp,Vj,0x10,Ri,0x15A515A5,0x15A515A5,0x15A515A5,0x15A515A5);
	switch (type) {
	  case 0: /* VADD */
	    for (m=0; m<8; m++)
		*(&VReg[Vk][0].u.h.hw+m) = *(&VReg[Vi][0].u.h.hw+m)
		    + *(&VReg[Vj][0].u.h.hw+m) + ((VCR[VCO]>>m)&1);
	    VCR[VCO] = 0;
	    break;
	  case 1: /* VADDC */
	  case 2: /* for appended CTC2 */
	    VCR[VCO] = 0;
	    for (m=0; m<8; m++) {
		tmp = *(&VReg[Vi][0].u.h.hw+m) + *(&VReg[Vj][0].u.h.hw+m);
		*(&VReg[Vk][0].u.h.hw+m) = tmp & 0xFFFF;
		VCR[VCO] |= (tmp&0x10000) >> (16-i); 
	    }
	    break;
	}
	
	fpLDVREG(outp,Vk,0x20,Ri,
		 VReg[Vk][0].w,VReg[Vk][1].w,VReg[Vk][2].w,VReg[Vk][3].w);

	Dadr += 3*0x10;

	fpCTC2(outp,Rj,VCO);			/* init VCO to $2	*/
	fpNOP(outp);
	fpNOP(outp);
	if ((IP&1 && !align) || (!(IP&1) && align))	fpNOP(outp);
	switch (type) {
	  case 0:
	    /****************************************************
	      Test that the correct VCO is used and the correct
	      value end up in the VCO register
	     ****************************************************/
	    fpCTC2(outp,Rk,VCO);
	    for (m=0; m<space; m++) fpNOP(outp);
	    fpVADD(outp,Vi,Vi,Vj);
	    for (m=0; m<space; m++) fpNOP(outp);
	    fpCTC2(outp,Rj,VCO);
	    break;
	  case 1:
	    /****************************************************
	      Make sure the VCO generated by VADDC overwrites
	      the CTC2.
	     ****************************************************/
	    fpCTC2(outp,Rk,VCO);
	    for (m=0; m<space; m++) fpNOP(outp);
	    fpVADDC(outp,Vi,Vi,Vj);
	    break;
	  case 2:
	    /****************************************************
	      Make sure the VCO written by CTC2 overwrites that
	      generated by VADDC.
	     ****************************************************/
	    fpCTC2(outp,Rk,VCO);		/* write $k into VCO	*/
	    for (m=0; m<space; m++) fpNOP(outp);
	    fpVADDC(outp,Vi,Vi,Vj);		/* use VCO		*/
	    for (m=0; m<space; m++) fpNOP(outp);
	    fpCTC2(outp,Rj,VCO);		/* write $j into VCO	*/
	    break;
	}
	fpNOP(outp);

	fpCTC2(outp,R0,VCC);			/* clear VCC		*/
	fpCFC2(outp,Rh,VCO);			/* read VCO		*/
	fpORI(outp,Rg,VCR[VCO]);		/* load predicted VCO	*/
	fpBNE(outp,Rg,Rh);	fpNOP(outp);	/* check for correctness*/

	fpVEQ(outp,Vj,Vi,Vk);			/* compare vector result*/
	fpORI(outp,Rg,VCR[VCC]);		/* load predicted VCC	*/
	fpCFC2(outp,Rh,VCC);			/* read VCC		*/
	fpBNE(outp,Rg,Rh);	fpNOP(outp);	/* check for correctness*/

    } /* TestBody */

    Tail(outp);

} /* GenCtlHz */

/************************************************************************
  DUAL-ISSUE TESTS:

  1. Normal dual-issue test: even alignment.
  2. Normal dual-issue test: odd  alignment.
  3. Normal dual-issue test: with bunching, even alignment.
  4. Normal dual-issue test: with bunching, odd  alignment.
  5. VU register hazard test.
  6. VU load-store dmem contention.
  7. VU control register (VCC, VCO, VCE) hazard test.
  
 ************************************************************************/
main()
{
    int i, j, k;
    FILE *script;

    if ((script = fopen("di.src", "w")) == NULL)
	fprintf(stderr,"ERR: Opening file %s failed.\n", cTFName);

    fprintf(script,"silent\n");

    /************************************************************
      1. GENERATE NORMAL DUAL-ISSUE TEST WITH EVEN ALIGNMENT
      2. GENERATE NORMAL DUAL-ISSUE TEST WITH ODD ALIGNMENT
      3. GENERATE NORMAL DUAL-ISSUE BUNCHING WITH EVEN ALIGNMENT
      4. GENERATE NORMAL DUAL-ISSUE BUNCHING WITH ODD ALIGNMENT
     ************************************************************/
    for (i=0; i<4; i++) {
	for (j=0; j<4; j++) {
	    sprintf(cTFName, "di_norm%d%d.s",i,j);
	    if ((fhTFile = fopen(cTFName, "w")) == NULL)
		fprintf(stderr,"ERR: Opening file %s failed.\n", cTFName);
	    GenNorm(fhTFile, j, i);
	    fclose(fhTFile);
	    fprintf(script,"load di_norm%d%d.bin 0x%8.8lX\n",j,i,IMEM_BASE);
	    fprintf(script,"load di_norm%d%d.dat 0x%8.8lX\n",j,i,DMEM_BASE);
	    fprintf(script,"dep PC 0x%8.8lX\nrun\nreg\n\n",IMEM_BASE-IMEM_BASE);
	}
    }

    /************************************************************
      5. GENERATE VU REG HAZARD TEST.
     ************************************************************/
    for (i=0; i<4; i++) {
	sprintf(cTFName, "di_reghz%d.s",i);
	if ((fhTFile = fopen(cTFName, "w")) == NULL)
	    fprintf(stderr,"ERR: Opening file %s failed.\n", cTFName);
	GenRegHz(fhTFile, i);
	fclose(fhTFile);
	fprintf(script,"load di_reghz%d.bin 0x%8.8lX\n",i,IMEM_BASE);
	fprintf(script,"load di_reghz%d.dat 0x%8.8lX\n",i,DMEM_BASE);
	fprintf(script,"dep PC 0x%8.8lX\nrun\nreg\n\n",IMEM_BASE-IMEM_BASE);
    }

    /************************************************************
      6. GENERATE VU LOAD-STORE DMEM CONTENTION TEST.
     ************************************************************/
    for (i=0; i<4; i++) {
	for (j=0; j<4; j++) {
	    sprintf(cTFName, "di_ldst%d%d.s",i,j);
	    if ((fhTFile = fopen(cTFName, "w")) == NULL)
		fprintf(stderr,"ERR: Opening file %s failed.\n", cTFName);
	    GenLdSt(fhTFile, i, j);
	    fclose(fhTFile);
	    fprintf(script,"load di_ldst%d%d.bin 0x%8.8lX\n",i,j,IMEM_BASE);
	    fprintf(script,"load di_ldst%d%d.dat 0x%8.8lX\n",i,j,DMEM_BASE);
	    fprintf(script,"dep PC 0x%8.8lX\nrun\nreg\n\n",IMEM_BASE-IMEM_BASE);
	}
    }

    /************************************************************
      7. GENERATE VU REG WITH LOAD-STORE HAZARDS.
     ************************************************************/
    for (k=0; k<2; k++) { /* space */
	for (i=0; i<2; i++) { /* align */
	    for (j=0; j<3; j++) { /* type */
		sprintf(cTFName, "di_ctlhz%d%d%d.s",k,i,j);
		if ((fhTFile = fopen(cTFName, "w")) == NULL)
		    fprintf(stderr,"ERR: Opening file %s failed.\n", cTFName);
		GenCtlHz(fhTFile,k,i,j);
		fclose(fhTFile);
		fprintf(script,"load di_ctlhz%d%d%d.bin 0x%8.8lX\n",k,i,j,IMEM_BASE);
		fprintf(script,"load di_ctlhz%d%d%d.dat 0x%8.8lX\n",k,i,j,DMEM_BASE);
		fprintf(script,"dep PC 0x%8.8lX\nrun\nreg\n\n",IMEM_BASE-IMEM_BASE);
	    }
	}
    }
    fprintf(script,"q\n");
    fclose(script);

} /* main */