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/************************************************************************
DMA BLOCK WRITE TESTS: File #5
************************************************************************/
.word 0x225D15EF
.word 0x18A77B21
.word 0x763B525D
.word 0x4F4C2F40
.word 0x2AFF50CE
.word 0x58B575FC
.word 0x09D26DC9
.word 0x59551AFD
.word 0x739D5D67
.word 0x272F0233
.word 0x7C5772AE
.word 0x34004491
.word 0x6F0F00AD
.word 0x6E2C5C8B
.word 0x06B8315B
.word 0x44691E50
.word 0x67B86E30
.word 0x382D77C7
.word 0x262F3681
.word 0x2AD8344B
.word 0x65077F9C
.word 0x51A14027
.word 0x59C07AA8
.word 0x7C4227D0
.word 0x40F95C39
.word 0x1A634EE5
.word 0x0FBD01B6
.word 0x2BC81AE7
.word 0x6D93106B
.word 0x07390DB8
.word 0x43446A6D
.word 0x24350BD5
.word 0x6A6A1531
.word 0x53554A53
.word 0x49BD6DEB
.word 0x1182209B
.word 0x6A1D47A8
.word 0x61D639E5
.word 0x505F4F2A
.word 0x5A536275
.word 0x27D75087
.word 0x4F466C98
.word 0x09AA3A80
.word 0x4979695D
.word 0x6CD07BA2
.word 0x331B3114
.word 0x0AEB151E
.word 0x67707788
.word 0x45CB7F69
.word 0x113967FC
.word 0x59BE3C94
.word 0x03E104E6
.word 0x68983469
.word 0x7B6C476D
.word 0x29853649
.word 0x6F1F3AA4
.word 0x49913CC8
.word 0x62F00E84
.word 0x48F44F05
.word 0x63AC5EAB
.word 0x611F1BCB
.word 0x19EA28D7
.word 0x3F872A69
.word 0x1FB32F21
.word 0x21343D51
.word 0x04EE41F9
.word 0x1B084273
.word 0x2E8E2DE5
.word 0x1AD06D57
.word 0x7C7A48F9
.word 0x6D0C56FC
.word 0x623F5C15
.word 0x537F3F74
.word 0x5E7863E1
.word 0x78754D3C
.word 0x7CF96589
.word 0x4AD7665D
.word 0x4FBE5339
.word 0x0EEF7F43
.word 0x0A963C57
.word 0x2FFC7B60
.word 0x2D8F4584
.word 0x1E757B80
.word 0x6A202450
.word 0x471D35EB
.word 0x2F191ABF
.word 0x6ECC343C
.word 0x074B2E80
.word 0x7EF71304
.word 0x36F717E7
.word 0x0F041F1E
.word 0x43F724AF
.word 0x36506CD0
.word 0x54AE0A72
.word 0x72FC44A6
.word 0x11B164E4
.word 0x317B020F
.word 0x76325BD3
.word 0x40DC3FB4
.word 0x3B302CDF
.word 0x3FD86D9C
.word 0x496114F9
.word 0x4E9B2D01
.word 0x5DDA559C
.word 0x11520DEF
.word 0x4D8451CE
.word 0x4F790AA2
.word 0x133F7ED5
.word 0x3BE25C9D
.word 0x14D324BA
.word 0x3184078A
.word 0x4A9B2A7F
.word 0x710935D5
.word 0x35F06A1F
.word 0x2B154306
.word 0x5256484A
.word 0x63580FE2
.word 0x6D690BDD
.word 0x78527C41
.word 0x11863123
.word 0x5BE922AE
.word 0x6F3834CE
.word 0x48AC31C1
.word 0x716912B3
.word 0x7FE57F3B
.word 0x68457449
.word 0x5C6130E6
.word 0x76ED4ADF
.word 0x45FE172A
.word 0x2FE151A1
.word 0x51F9156F
.word 0x0C2A3349
.word 0x1BF53436
.word 0x294A4FA4
.word 0x23CA38F7
.word 0x79E45CCB
.word 0x3C135FB8
.word 0x552B601F
.word 0x55761272
.word 0x110C3B01
.word 0x32B13A23
.word 0x131B4756
.word 0x516A05B2
.word 0x043F3FBE
.word 0x13B34287
.word 0x131C6F8F
.word 0x765E22E7
.word 0x71436693
.word 0x60070E10
.word 0x771C2C86
.word 0x54DA5618
.word 0x1A8F304E
.word 0x1B286F86
.word 0x24756EF8
.word 0x1CAE06AD
.word 0x50C20E77
.word 0x109F0ECC
.word 0x456E681B
.word 0x3A7726E7
.word 0x0C283ED2
.word 0x497F7063
.word 0x7ABA1D22
.word 0x251E3364
.word 0x363A16E2
.word 0x31E66CE7
.word 0x3CF66ABC
.word 0x5B5A229E
.word 0x231D3F62
.word 0x6E81188F
.word 0x6E2D7893
.word 0x112B446B
.word 0x3B205FCC
.word 0x62061AAF
.word 0x1B561CCF
.word 0x0D60117C
.word 0x544139D5
.word 0x62B97537
.word 0x6DD22F92
.word 0x37106AE0
.word 0x3BA734ED
.word 0x1FEA3C33
.word 0x4CF14E7C
.word 0x53224981
.word 0x6F2759C1
.word 0x37743D4B
.word 0x2F6C1026
.word 0x71C85DA3
.word 0x06C13DBA
.word 0x7B3E1743
.word 0x1CEA27A9
.word 0x0BFD1E6A
.word 0x4E225E7D
.word 0x66BC417A
.word 0x5F7E7817
.word 0x510C4953
.word 0x0E216D6B
.word 0x446C036D
.word 0x652517FF
.word 0x240B51B8
.word 0x06440B21
.word 0x035B5C33
.word 0x514A44EB
.word 0x495A404E
.word 0x163B72F8
.word 0x3C9F5A01
.word 0x3E4446E3
.word 0x442702A8
.word 0x17621684
.word 0x68DD61A5
.word 0x2ED443E9
.word 0x63EB2AB4
.word 0x66412916
.word 0x45C3660C
.word 0x2FA9037D
.word 0x01EC1E3B
.word 0x1C0E1B3B
.word 0x6B8D0FBF
.word 0x28DE2218
.word 0x6EBA3663
.word 0x7827063D
.word 0x12825460
.word 0x5F7934B3
.word 0x0FB44F2F
.word 0x799A07A0
.word 0x08757E2F
.word 0x26ED5C40
.word 0x2C8346FB
.word 0x289F0CA4
.word 0x56472389
.word 0x4296492D
.word 0x6C9C6E03
.word 0x101A0DC8
.word 0x15620E65
.word 0x77412EE7
.word 0x04C165DB
.word 0x671D3A42
.word 0x753D13D8
.word 0x4CA42752
.word 0x147E70F6
.word 0x6A62138A
.word 0x70DD5B91
.word 0x7EE00654
.word 0x33AE3221
.word 0x65D278CF
.word 0x3450175B
.word 0x20041D49
.word 0x2FF55C07
.word 0x6E03227E
.word 0x32322AA0
.word 0x698B6E8E
.word 0x7A4650AD
.word 0x49B40DC0
.word 0x692A41E2
.word 0x3DDB50F9
.word 0x445D30F5
.word 0x0B5157FA
.word 0x596C5A42
.word 0x59C6035C
.word 0x4E435C1E
.word 0x5A740A4D
.word 0x2A3638FB
.word 0x360B3008
.word 0x63CF5F40
.word 0x6D5F5516
.word 0x7F5552E5
.word 0x18D46046
.word 0x0A2154D2
.word 0x32853B6D
.word 0x7EA023F5
.word 0x57375FDE
.word 0x5D273425
.word 0x2A002EA8
.word 0x057A76BA
.word 0x46B71092
.word 0x1D1A10E8
.word 0x6F1A19D7
.word 0x0E521BE0
.word 0x5EC22DA2
.word 0x6C004AA5
.word 0x71C75D48
.word 0x462411AE
.word 0x0A337F47
.word 0x3B2A2C41
.word 0x60273A02
.word 0x51F71B8A
.word 0x28CF7E3A
.word 0x68B57B7E
.word 0x40072D4C
.word 0x445F4972
.word 0x40CA672D
.word 0x0D0B787A
.word 0x385F3C25
.word 0x42FB6F82
.word 0x60423E4E
.word 0x78624D2E
.word 0x0AD32ECC
.word 0x5BF60D73
.word 0x2EC142CA
.word 0x60396CF2
.word 0x3D343C38
.word 0x0B882618
.word 0x2EBD5245
.word 0x3CE063F6
.word 0x72FE259E
.word 0x717306E1
.word 0x2F183C64
.word 0x56EF16C9
.word 0x76D941F0
.word 0x36897F5A
.word 0x6CA20646
.word 0x04CB71D4
.word 0x741A795A
.word 0x222308AB
.word 0x63951E05
.word 0x182708DE
.word 0x604230C5
.word 0x5FA95D18
.word 0x51167E37
.word 0x7B7F2688
.word 0x147C2556
.word 0x740F7F80
.word 0x64B94171
.word 0x7F9D4BCF
.word 0x172137EE
.word 0x635432DF
.word 0x21FC25C0
.word 0x59151F8F
.word 0x153528A9
.word 0x060361CE
.word 0x71C80031
.word 0x4DCB4DFC
.word 0x0BE94262
.word 0x0EB47601
.word 0x63F52048
.word 0x126A5829
.word 0x221A762C
.word 0x3F8A1FC6
.word 0x20C5238A
.word 0x57EC5384
.word 0x31CE66D8
.word 0x4FB40D8A
.word 0x0A6638F6
.word 0x09181956
.word 0x01BC6473
.word 0x00EE1355
.word 0x0E725486
.word 0x37FD6645
.word 0x2EC357C7
.word 0x6500424B
.word 0x277052B0
.word 0x3B7969D3
.word 0x456F1DD7
.word 0x533C702B
.word 0x0E530BE9
.word 0x7CB745DF
.word 0x0B7A5366
.word 0x0E022ED2
.word 0x1BF8581E
.word 0x74AA7E21
.word 0x7946106F
.word 0x183D33B8
.word 0x5AAB023B
.word 0x599557B0
.word 0x636613AC
.word 0x3AE52F6F
.word 0x47A02BA7
.word 0x7C85287E
.word 0x54155E11
.word 0x3A7D1528
.word 0x447C1FC4
.word 0x56D316D8
.word 0x14BB3E50
.word 0x3C945230
.word 0x38CC1772
.word 0x47A448E9
.word 0x676D4C54
.word 0x5D47756D
.word 0x638A6C8A
.word 0x016B0436
.word 0x706B54C9
.word 0x74BB46E4
.word 0x5C9D3D65
.word 0x27643D21
.word 0x4FA13491
.word 0x0CA54F35
.word 0x46570054
.word 0x1B191668
.word 0x6A29244D
.word 0x05C44F1B
.word 0x2EF80728
.word 0x79DF50A5
.word 0x63C673DC
.word 0x6D6426EE
.word 0x222872AA
.word 0x4A5829CE
.word 0x486935D5
.word 0x02DB2E23
.word 0x6A7E1622
.word 0x59F02CB4
.word 0x65AE5B0E
.word 0x6D0D7AC9
.word 0x02FE4AD2
.word 0x4A627086
.word 0x545E3E17
.word 0x1FE9190B
.word 0x38943379
.word 0x4F32484E
.word 0x31EC1EBE
.word 0x71EC32B3
.word 0x7B9C6FD3
.word 0x1B326270
.word 0x09F90D8A
.word 0x619B26A3
.word 0x615C4015
.word 0x7E005830
.word 0x6FD24742
.word 0x0B0B105C
.word 0x55871874
.word 0x31852D2B
.word 0x47F00065
.word 0x4D5C3F79
.word 0x7BBA249D
.word 0x57753EDB
.word 0x417520B1
.word 0x20371F33
.word 0x41003B3C
.word 0x26D32415
.word 0x7FB36E9F
.word 0x19550DDD
.word 0x1D4F4178
.word 0x496C7C8C
.word 0x73A62AE3
.word 0x21F92467
.word 0x050A7E73
.word 0x695A304E
.word 0x65771BEF
.word 0x5C736DDD
.word 0x0A805ECC
.word 0x6E801F44
.word 0x2DFA096E
.word 0x399E0EE7
.word 0x2F6A281F
.word 0x6C1240B4
.word 0x202F27CB
.word 0x3E605D48
.word 0x666F1C81
.word 0x3E0D32C1
.word 0x22C273AA
.word 0x792E6761
.word 0x44A10E07
.word 0x56B939E8
.word 0x798D7D6C
.word 0x27886BAE
.word 0x62FF623E
.word 0x3C2C3082
.word 0x3F1224AE
.word 0x0B774045
.word 0x6FF205B2
.word 0x35C86646
.word 0x0E0443C8
.word 0x71142A5D
.word 0x70D34F6A
.word 0x29B96FC6
.word 0x5ABD4B50
.word 0x640325C3
.word 0x33625468
.word 0x2A7A65F0
.word 0x7CC84D96
.word 0x14F11C64
.word 0x6F4E2B2B
.word 0x3450158C
.word 0x68577A27
.word 0x6F1C0DC8
.word 0x17B21F2F
.word 0x1ACB1EC2
.word 0x17CB094C
.word 0x5DCA2693
.word 0x5C935469
.word 0x264A0494
.word 0x2531178B
.word 0x41CE4804
.word 0x5C655ACE
.word 0x61762C5E
.word 0x13C07123
.word 0x17097F78
.word 0x058631CB
.word 0x16C34D5B
.word 0x495E4D92
.word 0x49E46DE6
.word 0x27C03BCC
.word 0x7DF55021
.word 0x381B7B11
.word 0x3CD81F62
.word 0x35C921B8
.word 0x19971E22
.word 0x37B37A14
.word 0x7DE9529C
.word 0x36C42671
.word 0x4483612B
.word 0x0F0F08CC
.word 0x2C253061
.word 0x67BF6A56
.word 0x6F6032E6
.word 0x2DC21EA7
.word 0x0D277317
.word 0x0D351EC2
.word 0x0E1D3C5A
.word 0x158E57CD
.word 0x52987E43
.word 0x748B298D
.word 0x35784568
.word 0x73DE50A3
.word 0x0FAB6604
.word 0x25953888
.word 0x687B344E
.word 0x6B4B714A
.word 0x5E9E6697
.word 0x44104504
.word 0x15FC7D26
.word 0x0D19291E
.word 0x363E4BD4
.word 0x2128074A
.word 0x461B0166
.word 0x02BA1A39
.word 0x6F6148AD
.word 0x7CF25A21
.word 0x77C55F5F
.word 0x674834F0
.word 0x7A6C3EB4
.word 0x77F10E4D
.word 0x2E3531C0
.word 0x510D4353
.word 0x44CD7593
.word 0x34932E0C
.word 0x2E703F12
.word 0x0AFC64AF
.word 0x4E7F4294
.word 0x28B2309A
.word 0x6CC7193C
.word 0x7E37790E
.word 0x6F8B2019
.word 0x1F151DAC
.word 0x2A572CFE
.word 0x4B8A7CB3
.word 0x4D843522
.word 0x68EF20F7
.word 0x428A4178
.word 0x14EC53A0
.word 0x01084CCD
.word 0x3F5E0DA8
.word 0x289567A3
.word 0x77030512
.word 0x6B443DCF
.word 0x54EB51EB
.word 0x14F959D4
.word 0x329F6702
.word 0x3B6F41FE
.word 0x170E5A66
.word 0x63054B3E
.word 0x063B39A4
.word 0x244B3DC9
.word 0x1FA865BD
.word 0x1E50276F
.word 0x378132E9
.word 0x41A977BC
.word 0x5689480F
.word 0x404241D0
.word 0x4CC579FF
.word 0x2DE43FFE
.word 0x42EA1E75
.word 0x1D8A7527
.word 0x768812CE
.word 0x476307D5
.word 0x0CF37288
.word 0x03A73316
.word 0x28F4397B
.word 0x261A691E
.word 0x2F344DD9
.word 0x0661039C
.word 0x65642DE7
.word 0x41081DD8
.word 0x582D3D78
.word 0x7D4F7491
.word 0x33DB6F2E
.word 0x43B76799
.word 0x7BC94570
.word 0x3151792C
.word 0x4C8A672A
.word 0x13C16715
.word 0x14DC4447
.word 0x3A15397F
.word 0x714D05F0
.word 0x0648639C
.word 0x16AB4681
.word 0x0B9451F7
.word 0x772D4D50
.word 0x457B029A
.word 0x0E624A1D
.word 0x339402DF
.word 0x7FDD4C57
.word 0x66166F16
.word 0x749D7214
.word 0x47264FDC
.word 0x633F0ACE
.word 0x2CE07136
.word 0x2EE329DE
.word 0x00270F70
.word 0x48DE64BA
.word 0x042D75B8
.word 0x412438EF
.word 0x0AC16A79
.word 0x717355DC
.word 0x215B0579
.word 0x2F404634
.word 0x02E94BB1
.word 0x30623531
.word 0x5A572CF0
.word 0x0E814B99
.word 0x21E13F2E
.word 0x153D6072
.word 0x2B1853B1
.word 0x471E7984
.word 0x1BB541E2
.word 0x453E5793
.word 0x6B2103EC
.word 0x05B80A59
.word 0x2CC0011A
.word 0x04CF4845
.word 0x330121ED
.word 0x5CDE05F6
.word 0x57270A00
.word 0x71040976
.word 0x71D4139C
.word 0x168B7537
.word 0x505A691B
.word 0x691C06CE
.word 0x32C157FD
.word 0x35A50571
.word 0x1E9839CC
.word 0x28061C32
.word 0x127C0EB0
.word 0x277E1BF8
.word 0x666A25D1
.word 0x0DD86142
.word 0x64C46F6F
.word 0x2555599C
.word 0x682454C3
.word 0x195864DD
.word 0x09E43195
.word 0x45D40E25
.word 0x2D6A4B9A
.word 0x1176589A
.word 0x74346393
.word 0x3E921BDD
.word 0x66A73C26
.word 0x5ECE2C4E
.word 0x5D97327B
.word 0x55904B05
.word 0x78954496
.word 0x1528198B
.word 0x2CFC2177
.word 0x02BD0D5C
.word 0x39BA1EF3
.word 0x2CF91F1D
.word 0x0BDF3150
.word 0x4174319D
.word 0x5FE740A3
.word 0x6CE16C8D
.word 0x2BC877EA
.word 0x11FB06FF
.word 0x1DBA69E9
.word 0x032D3DA1
.word 0x3BC827C5
.word 0x2B0470B6
.word 0x701B2561
.word 0x4F5525D8
.word 0x0E01077C
.word 0x5B2D696F
.word 0x1BC03787
.word 0x5B7D4BF0
.word 0x6D1D5947
.word 0x1A8276D6
.word 0x5AAB7E2F
.word 0x05F61561
.word 0x21D4327B
.word 0x4BF80D11
.word 0x39A9400C
.word 0x5ABC41E1
.word 0x28694307
.word 0x2EF26244
.word 0x25D36C2C
.word 0x1CF776E0
.word 0x162C0CF6
.word 0x00BE320D
.word 0x2A0F4977
.word 0x007D3B0C
.word 0x2EF70BF2
.word 0x4E177107
.word 0x5C8D1636
.word 0x134C61CD
.word 0x2AB24CBD
.word 0x74A3704A
.word 0x7C4C1788
.word 0x571366C7
.word 0x2AD174B8
.word 0x547470E7
.word 0x3E9518EC
.word 0x0AA8395D
.word 0x5FD3395E
.word 0x3188276E
.word 0x4C7D5BBC
.word 0x2390782A
.word 0x5EC447C8
.word 0x454B2F6A
.word 0x706676AE
.word 0x777D1C88
.word 0x26BA1C29
.word 0x00126EE1
.word 0x737C2554
.word 0x15C9160C
.word 0x56594950
.word 0x7AA069D7
.word 0x2B39079B
.word 0x50FE5605
.word 0x1150302B
.word 0x17A305CA
.word 0x36E4514E
.word 0x78504B02
.word 0x15DC2741
.word 0x55353D35
.word 0x6D0C6992
.word 0x411F4C4C
.word 0x02421236
.word 0x4E5E430F
.word 0x79107A69
.word 0x60777566
.word 0x4A576949
.word 0x6C8E164C
.word 0x28987031
.word 0x54927192
.word 0x5CFA30D6
.word 0x49260559
.word 0x691B6924
.word 0x5E52374D
.word 0x799760D6
.word 0x3EEE21A2
.word 0x755914D7
.word 0x2ACA33CF
.word 0x35A43C5C
.word 0x2B9E230D
.word 0x32E003BE
.word 0x2CB5668E
.word 0x32251918
.word 0x61583B7E
.word 0x3F8966A5
.word 0x25FB6CBA
.word 0x012916D6
.word 0x482A5A53
.word 0x2EFA3E36
.word 0x61317CC1
.word 0x3B4D46FE
.word 0x2F8E5FE7
.word 0x78237A77
.word 0x1B1751CA
.word 0x45364414
.word 0x4FEB4111
.word 0x12C40A4B
.word 0x1C1A073C
.word 0x451A3937
.word 0x7C141AA4
.word 0x44E45AEF
.word 0x01D26437
.word 0x483659A4
.word 0x02C634EF
.word 0x2059477C
.word 0x38831717
.word 0x18564832
.word 0x402C773D
.word 0x3044786A
.word 0x249E60F6
.word 0x41526ED5
.word 0x5F5D4B54
.word 0x56943309
.word 0x7C3F3128
.word 0x468E461D
.word 0x4BDB70F8
.word 0x59811908
.word 0x50AF30BF
.word 0x08770CB7
.word 0x53134167
.word 0x211057F0
.word 0x47E13E07
.word 0x5A0B6EE9
.word 0x75E162DC
.word 0x249448A7
.word 0x05F75809
.word 0x46501E18
.word 0x6A0C6C0F
.word 0x08297EEF
.word 0x46BC7A0A
.word 0x05D95843
.word 0x4BC477B1
.word 0x6A3848E7
.word 0x2729670B
.word 0x24465F87
.word 0x7F2927F2
.word 0x60F81E87
.word 0x1EE36549
.word 0x55C3619B
.word 0x41C519FC
.word 0x27E90126
.word 0x29B969BC
.word 0x7C864F54
.word 0x6C0F4978
.word 0x7D594AF6
.word 0x2129339A
.word 0x5E532420
.word 0x62E86406
.word 0x2FE26E84
.word 0x45DA57D3
.word 0x09FA1D8D
.word 0x39200CC7
.word 0x5BE8263B
.word 0x79203C95
.word 0x6CD662C1
.word 0x00F00FD5
.word 0x591D13E0
.word 0x267D04C7
.word 0x184E1C02
.word 0x4D7F05C8
.word 0x57FE5015
.word 0x5D1D6B90
.word 0x37557A2D
.word 0x645F6731
.word 0x2F5569D8
.word 0x19570FCF
.word 0x33EB2E40
.word 0x1F0F1020
.word 0x59B85604
.word 0x3E312FA3
.word 0x0C9C50D3
.word 0x7C79339F
.word 0x23064ECC
.word 0x3EDB53E2
.word 0x59FE3999
.word 0x62733F37
.word 0x05EF2345
.word 0x78316BA4
.word 0x043646E1
.word 0x0F412E68
.word 0x396B76DB
.word 0x3A3B57B7
.word 0x28721519
.word 0x3B0F4E33
.word 0x6E4070D8
.word 0x01AE662A
.word 0x2E6D2648
.word 0x69797092
.word 0x3C7E5BE3
.word 0x616A3DC5
.word 0x0DF07991
.word 0x6B050FFD
.word 0x4104357D
.word 0x1BFC398D
.word 0x444E12B5
.word 0x0EA562E5
.word 0x6AFB2D84
.word 0x6D1C3443
.word 0x79E5718F
.word 0x03385F3A
.word 0x795815B2
.word 0x032E43E4
.word 0x57A27998
.word 0x69072DE6
.word 0x285D411C
.word 0x28C36528
.word 0x0C7B4963
.word 0x134B0E51
.word 0x0F1653B6
.word 0x1E181705
.word 0x02F50220
.word 0x79A429DE
.word 0x2CDD01CB
.word 0x2293662B
.word 0x469E7F1B
.word 0x59A1576B
.word 0x26D93F87
.word 0x2E4B6888
.word 0x19927D3C
.word 0x083D4ED3
.word 0x35796070
.word 0x5B7E28C3
.word 0x39F83286
.word 0x735D4C6D
.word 0x41FB26E7
.word 0x001B01C3
.word 0x5783559A
.word 0x5355248C
.word 0x33EA43A9
.word 0x77386A27
.word 0x38F41534
.word 0x0C6346FF
.word 0x6E994552
.word 0x1A9A2FCD
.word 0x11957FAB
.word 0x40313291
.word 0x7EAB77D6
.word 0x6C33234E
.word 0x06BD5A73
.word 0x0F555888
.word 0x778D3408
.word 0x6F9D337E
.word 0x6551699C
.word 0x0AD27028
.word 0x00F81F15
.word 0x33A278EF
.word 0x073F2752
.word 0x55963A2E
.word 0x14725A08
.word 0x0BB6316D
.word 0x69036B5D
.word 0x75FB3457
.word 0x6ACC2146
.word 0x79792B81
.word 0x6F2402A1
.word 0x57493CDA
.word 0x19A35C12
.word 0x463721F0
.word 0x5BB5369E
.word 0x7B3125E8
.word 0x60E11C08
.word 0x4C6A073A
.word 0x73D744EE
.word 0x5B513931
.word 0x283B0CA3
.word 0x7135411E
.word 0x553446CC
.word 0x7AB52B5F
.word 0x2CB352B9
.word 0x4DE95413
.word 0x7B840889
.word 0x27517F9A
.word 0x5E165BFC
.word 0x09817ECF
.word 0x76095116
.word 0x6B8A5B05
.word 0x6C7C1E79
.word 0x622845C2
.word 0x4D141980
.word 0x2FAD483E
.word 0x05CD481B
.word 0x66B06E99
.word 0x1780346D
.word 0x0B746AE0
.word 0x43385E27
.word 0x601A6BBE
.word 0x403565A2
.word 0x47872302
.word 0x46BC4CBF
.word 0x6B1337D4
.word 0x7BA4697F
.word 0x0EF720B7
.word 0x08A16661
.word 0x4173213E
.word 0x6D4F6C7F
.word 0x50C2678E
.word 0x54FE5367
.word 0x33BE0597
.word 0x7D4072BA
.word 0x51534211
.word 0x79337187
.word 0x52A57D38
.word 0x5D8F2F65
.word 0x6C012548
.word 0x216E2352
.word 0x488576B8
.word 0x3FDF4C4E
.word 0x048E0436
.word 0x66290FB7
.word 0x62E44265
.word 0x3ADF2163
.word 0x28A71359
.word 0x09A8517F
.word 0x4BF90DCE
.word 0x5FCB5C2A
.word 0x61697C2C
.word 0x657D16D1
.word 0x74224F3B
.word 0x7FEA1748
.word 0x34D800A6
.word 0x080530AD
.word 0x2B6E2131
.word 0x221061FD
.word 0x57670EBA
.word 0x01EA1273
.word 0x6B130DF1
.word 0x281C37A5
.word 0x0D7543D6
.word 0x63A2415C
.word 0x4EF74AF7
.word 0x24796736
.word 0x3CCD6067
.word 0x6AEC33FD
.word 0x3F29647D
.word 0x5F9F6AC6
.word 0x2E232B52
.word 0x605821CA
.word 0x496658F8
.word 0x0D912F04
.word 0x7E9C457B
.word 0x24BE428E
.word 0x2A972498
.word 0x335E4ABC
.word 0x41446D3F
.word 0x6EC47DF5
.word 0x08503CCA
.word 0x3CA22655
.word 0x509731FB
.word 0x385A0B04
.word 0x5A517BB8
.word 0x41051355
.word 0x4FFB1785
.word 0x5C3F7F9E
.word 0x04077BC5
/****************************************************************
DMA TEST #5.61
****************************************************************/
ori $1, $0, 0x003D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $13, 0x0A00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x207F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
Prep61: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep61 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont61 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep61 /* go look */
Cont61:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write61: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write61 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x79B9 /* load random number */
ori $9, $9, 0x53DA
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x007C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read61: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read61 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk61: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk61 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done61 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk61 /* go loop */
Done61:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln61: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln61 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.62
****************************************************************/
ori $1, $0, 0x003E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F70 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x007F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep62: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep62 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont62 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep62 /* go look */
Cont62:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write62: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write62 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5D43 /* load random number */
ori $9, $9, 0x29B0
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read62: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read62 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk62: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk62 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done62 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk62 /* go loop */
Done62:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln62: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln62 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.63
****************************************************************/
ori $1, $0, 0x003F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0F78 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x007F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep63: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep63 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont63 /* exit loop if 0 span */
ori $3, $0, 0x0080 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep63 /* go look */
Cont63:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write63: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write63 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x637C /* load random number */
ori $9, $9, 0x4FFF
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x007C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read63: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read63 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk63: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk63 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done63 /* exit if zero span */
ori $3, $0, 0x0080 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk63 /* go loop */
Done63:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln63: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln63 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.64
****************************************************************/
ori $1, $0, 0x0040 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x0A80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x17F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A8 /* number of skips */
Prep64: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep64 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont64 /* exit loop if 0 span */
ori $3, $0, 0x07F8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep64 /* go look */
Cont64:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write64: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write64 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1E09 /* load random number */
ori $9, $9, 0x6313
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x07F4
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read64: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read64 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk64: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk64 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done64 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk64 /* go loop */
Done64:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln64: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln64 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.65
****************************************************************/
ori $1, $0, 0x0041 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0x0B00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x17F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00B0 /* number of skips */
Prep65: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep65 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont65 /* exit loop if 0 span */
ori $3, $0, 0x07F8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep65 /* go look */
Cont65:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write65 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x66FE /* load random number */
ori $9, $9, 0x1220
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x07F4
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read65 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00B0 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk65: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk65 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done65 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk65 /* go loop */
Done65:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln65: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln65 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.66
****************************************************************/
ori $1, $0, 0x0042 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0010 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2810
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep66: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep66 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont66 /* exit loop if 0 span */
ori $3, $0, 0x07F8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep66 /* go look */
Cont66:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write66 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x722C /* load random number */
ori $9, $9, 0x7FCB
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read66 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk66: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk66 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done66 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk66 /* go loop */
Done66:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln66: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln66 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.67
****************************************************************/
ori $1, $0, 0x0043 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep67: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep67 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont67 /* exit loop if 0 span */
ori $3, $0, 0x07F8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep67 /* go look */
Cont67:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write67 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x02E6 /* load random number */
ori $9, $9, 0x3E43
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read67 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk67: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk67 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done67 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk67 /* go loop */
Done67:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln67: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln67 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.68
****************************************************************/
ori $1, $0, 0x0044 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07F7
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep68: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep68 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont68 /* exit loop if 0 span */
ori $3, $0, 0x07F8 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep68 /* go look */
Cont68:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write68 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x6F9D /* load random number */
ori $9, $9, 0x1EFF
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07F4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read68 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x07F8 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk68: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk68 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done68 /* exit if zero span */
ori $3, $0, 0x07F8 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk68 /* go loop */
Done68:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln68: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln68 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.69
****************************************************************/
ori $1, $0, 0x0045 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x0C00 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x17FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00C0 /* number of skips */
Prep69: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep69 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont69 /* exit loop if 0 span */
ori $3, $0, 0x0800 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep69 /* go look */
Cont69:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write69 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x259F /* load random number */
ori $9, $9, 0x4800
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x07FC
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read69 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00C0 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk69: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk69 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done69 /* exit if zero span */
ori $3, $0, 0x0800 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk69 /* go loop */
Done69:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln69: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln69 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.70
****************************************************************/
ori $1, $0, 0x0046 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep70: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep70 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont70 /* exit loop if 0 span */
ori $3, $0, 0x0800 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep70 /* go look */
Cont70:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write70 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x75E1 /* load random number */
ori $9, $9, 0x3021
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read70 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk70: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk70 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done70 /* exit if zero span */
ori $3, $0, 0x0800 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk70 /* go loop */
Done70:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln70: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln70 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.71
****************************************************************/
ori $1, $0, 0x0047 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep71: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep71 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont71 /* exit loop if 0 span */
ori $3, $0, 0x0800 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep71 /* go look */
Cont71:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write71 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x489E /* load random number */
ori $9, $9, 0x39DE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read71 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk71: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk71 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done71 /* exit if zero span */
ori $3, $0, 0x0800 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk71 /* go loop */
Done71:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln71 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #5.72
****************************************************************/
ori $1, $0, 0x0048 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x07FF
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep72: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep72 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont72 /* exit loop if 0 span */
ori $3, $0, 0x0800 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep72 /* go look */
Cont72:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write72 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x1833 /* load random number */
ori $9, $9, 0x0FA2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read72 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk72: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk72 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done72 /* exit if zero span */
ori $3, $0, 0x0800 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk72 /* go loop */
Done72:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln72 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break