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/************************************************************************
DMA READ TESTS: File #2
************************************************************************/
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/****************************************************************
DMA TEST #2.71
****************************************************************/
ori $1, $0, 0x0047 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read71: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read71 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk71: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk71 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x2387 /* load random number */
ori $9, $9, 0x7033
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.72
****************************************************************/
ori $1, $0, 0x0048 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x07FF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read72: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read72 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0800 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk72: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk72 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x3C2A /* load random number */
ori $9, $9, 0x3D2F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x07FC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.73
****************************************************************/
ori $1, $0, 0x0049 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read73: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read73 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk73: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk73 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x42B5 /* load random number */
ori $9, $9, 0x6F1D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.74
****************************************************************/
ori $1, $0, 0x004A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read74: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read74 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk74: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk74 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6D42 /* load random number */
ori $9, $9, 0x6DD2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.75
****************************************************************/
ori $1, $0, 0x004B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0807
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read75: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read75 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0808 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk75: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk75 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x0957 /* load random number */
ori $9, $9, 0x448E
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0804 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.76
****************************************************************/
ori $1, $0, 0x004C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x080F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read76: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read76 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0810 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk76: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk76 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x08C9 /* load random number */
ori $9, $9, 0x388A
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x080C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.77
****************************************************************/
ori $1, $0, 0x004D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FF7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read77: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read77 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk77: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk77 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x6F33 /* load random number */
ori $9, $9, 0x54B1
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.78
****************************************************************/
ori $1, $0, 0x004E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FF7
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read78: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read78 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x0FF8 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk78: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk78 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x7664 /* load random number */
ori $9, $9, 0x4BA6
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FF4 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
DMA TEST #2.79
****************************************************************/
ori $1, $0, 0x004F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0FFF
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read79: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read79 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
ori $3, $0, 0x1000 /* len of data (bytes) */
ori $6, $10, 0x0000 /* copy DMEM address */
Chk79: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
sub $3, $3, $2 /* decrement counter */
bne $3, $0, Chk79 /* check if done */
/* Mess up DMEM before reading data back */
lui $9, 0x1116 /* load random number */
ori $9, $9, 0x72E7
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0FFC /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break