gen.h
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/************************************************************************
WHAT: RSP REGRESSION TEST GENERATOR - DEFINITIONS
SCCS: @(#)gen.h 1.1 03 Aug 1994
PTLS: $Id: gen.h,v 1.1.1.1 2002/05/02 03:29:15 blythe Exp $
FILE: gen.h
ENGR: Project Reality - Evan Y. Wang
(CR): 1994 Silicon Graphics, Inc.
************************************************************************/
#ifndef _table_h_
#define _table_h_
#define IMEM_SIZE 0x1000 /* 4 KByte */
#define DMEM_SIZE 0x1000 /* 4 KByte */
/************************************************************************
GENERATOR RELATED DEFINITIONS
************************************************************************/
#define BMEMSIZE 128 /* number of byte-addressable memory */
#define HMEMSIZE 64 /* number of hword-addressable memory */
#define WMEMSIZE 32 /* number of word-addressable memory */
#define MEMSIZE 128 /* number of bytes in new memory model */
#define IMEM_BASE 0x04001000 /* really is 0x04001000 */
#define DMEM_BASE 0x04000000 /* really is 0x04000000 */
/************************************************************************
TEST CASE GENERATION RELATED DEFINITIONS
************************************************************************/
#define HEAD_NUMLINES 65 /* overhead */
#define END_NUMLINES 2 /* overhead */
#define VEC_INITS 32 /* overhead */
#define MAX_INSTR_PER_FILE ((IMEM_SIZE>>2)-HEAD_NUMLINES-END_NUMLINES)
#define MAX_VECINST_PER_FILE ((IMEM_SIZE>>2)-HEAD_NUMLINES-END_NUMLINES-VEC_INITS)
/************************************************************************
UTILITY MACRO FUNCTIONS:
HHW - Extract high half-word.
LHW - Extract low half-word.
UpdRegID - Update register IDs rT, rA, rB, and rR.
FILE_SPLIT - Used to split test program into multiple files.
************************************************************************/
#define HHW(op) (((op) >> 16) & 0xFFFF)
#define LHW(op) ((op) & 0xFFFF)
#define HSgnExt(x) ((u32)((x)&0xFFFF)|((x)&0x8000?~0xFFFF:0))
#define BSgnExt(x) (((x)&0xFF)|((x)&0x80?~0xFF:0))
#define UpdRegID() { rT=rA; rA=rB; rB=rR; rR=((rR-1)%29)+2; }
#define UpdVRegID() { vT=vA; vA=vB; vB=vC; vC=(vC+1)%32; }
#define UpdRegTABR() { Reg[rT]=Res; Reg[rR]=Res; \
Reg[rA]=OpA; Reg[rB]=OpB; }
#define UpdRegTBR() { Reg[rT]=Res; Reg[rR]=Res; Reg[rB]=OpB; }
#define UpdRegTAR() { Reg[rT]=Res; Reg[rR]=Res; Reg[rA]=OpA; }
#define UpdRegTA() { Reg[rT]=Res; Reg[rA]=OpA; }
#define UpdRegTR() { Reg[rT]=Res; Reg[rR]=Res; }
#define FILE_SPLIT \
if (CurTcNo - NxTcNo >= (MAX_TCS)) return CurTcNo; \
else if (NxTcNo <= CurTcNo)
typedef enum {
NUL_VEC, /* for those that don't need vec*/
ADD_VEC, /* addition vector type */
LOG_VEC, /* logic vector type */
BRN_VEC, /* branch vector type */
JMP_VEC, /* jump vector type */
LDB_VEC, /* load vector type */
LDH_VEC, /* load vector type */
LUI_VEC, /* load vector type */
LDW_VEC, /* load vector type */
STB_VEC, /* load vector type */
STH_VEC, /* load vector type */
STW_VEC, /* load vector type */
SET_VEC, /* set-on vector type */
SHF_VEC, /* shift vector type */
VLS_BYTE, /* vector load/store byte op */
VLS_SHRT, /* vector load/store short op */
VLS_WORD, /* vector load/store word op */
VLS_DBLE, /* vector load/store double op */
VLS_QUAD, /* vector load/store quad op */
VLS_REST, /* vector load/store rest op */
VLS_PACK, /* vector load/store pack op */
VLS_UPCK, /* vector load/store unpack op */
VLS_HALF, /* vector load/store half op */
VLS_FRTH, /* vector load/store fourth op */
VLD_TRNS, /* vector load/store transpose */
VST_TRNS, /* vector load/store transpose */
VST_WRAP /* vector store wrap */
} VECT_TYPE;
typedef enum {
NMEM, /* No memory model needed */
SMEM, /* memory model for scalar unit tests */
VMEM, /* memory model for vector unit tests */
ZMEM /* Zero'd memory model */
} MEM_TYPE;
typedef struct {
char *name; /* instruction string */
int mem; /* generate memory or not */
int vec; /* vector generation type */
int (*gen)(); /* test generator */
u32 (*proc)(); /* instruction model */
} I_TABLE;
typedef union {
u32 w; /* word */
struct { /* union within word */
union { /* high half-word */
u16 hw;
struct {
u8 hb; /* high byte of high half-word */
u8 lb; /* low byte of high half-word */
} u;
} h;
union { /* low half-word */
u16 hw;
struct {
u8 hb; /* high byte of low half-word */
u8 lb; /* low byte of low half-word */
} u;
} l;
} u;
} DATA;
/************************************************************************
PUBLIC SUBROUTINES
************************************************************************/
extern int AluWWWGen(); /* defined in alu_www.c */
extern int AluWWIGen(); /* defined in alu_wwi.c */
extern int AluWIGen(); /* defined in alu_wi.c */
extern int BrWWGen(); /* defined in br_ww.c */
extern int BrWGen(); /* defined in br_w.c */
extern int BrlWGen(); /* defined in brl_w.c */
extern int JGen(); /* defined in j.c */
extern int JalGen(); /* defined in jal.c */
extern int JalrGen(); /* defined in jalr.c */
extern int JrGen(); /* defined in jr.c */
extern int LdGen(); /* defined in ld.c */
extern int StGen(); /* defined in st.c */
extern int VldGen(); /* defined in vld.c */
extern int VstGen(); /* defined in vst.c */
/* extern int VltxGen(); /* defined in vltx.c */
/* extern int VstxGen(); /* defined in vstx.c */
extern int VtwGen(); /* defined in vtw.c */
extern int Cc2Gen(); /* defined in cc2.c */
extern int Mc2Gen(); /* defined in mc2.c */
/************************************************************************
GLOBAL VARIABLES
************************************************************************/
/* defined in table.c */
extern I_TABLE InstrTable[]; /* instruction table */
extern int InstrTableSize; /* instruction table size */
extern u8 * BMem[]; /* byte memory ptr array */
extern u16 * HMem[]; /* half-memory memory ptr array */
extern u32 * WMem[]; /* word memory ptr array */
/* defined in main.c */
extern DATA Mem[]; /* memory model */
extern DATA VReg[][4]; /* vector unit register file */
extern u32 Reg[]; /* scalar unit register file */
extern u32 Res; /* predicted result */
extern u32 OpA; /* input operand A */
extern u32 OpB; /* input operand B */
extern u32 Imm; /* immediate operand */
extern int rT; /* prediction reg ID */
extern int rA; /* operand A reg ID */
extern int rB; /* operand B reg ID */
extern int rR; /* destination reg ID */
extern int CurTcNo; /* current test case number */
extern int NxTcNo; /* next test case number */
extern int CntA; /* index used in enumerating OpA*/
extern int CntB; /* index used in enumerating OpB*/
extern int CntI; /* index used in enumerating Imm*/
extern int vT; /* target vector register ID */
extern int vA; /* test vector register A ID */
extern int vB; /* test vector register B ID */
extern int vC; /* test vector register C ID */
extern int El; /* element field */
extern u16 VCC; /* VCC register (mapped to v$1) */
extern u16 VCO; /* VCO register (mapped to v$0) */
#endif