`include "rsp_regr.h"

/****************************************************
 * $test$plusargs setups
 ***************************************************/
`ifdef REALITY_RSP_REGRESSION
`else
reg random_dma_mode;
initial
begin
  rsp_random_dma.random_idma_mode = 0;
  rsp_random_dma.random_ddma_mode = 0;
  rsp_random_dma.random_halt_mode = 0;
  random_dma_mode = 0;

  if ($test$plusargs("random_idma"))
      begin
        $display("setting random_idma_mode bit");
        rsp_random_dma.random_idma_mode = 1;
	random_dma_mode = 1;
      end
  if ($test$plusargs("random_ddma"))
      begin
        $display("setting random_ddma_mode bit");
        rsp_random_dma.random_ddma_mode = 1;
	random_dma_mode = 1;
      end
  if ($test$plusargs("random_halt"))
      begin
        $display("setting random_halt_mode bit");
        rsp_random_dma.random_halt_mode = 1;
	random_dma_mode = 1;
      end
  #1
  if (random_dma_mode)
      rsp_random_dma.fp = $fopen("random_dma.log");

  #10
  rsp_random_dma.seed = 32'h00000005;
  if ($getnum$plusarg("seed=", rsp_random_dma.seed) == 1)
   begin
   end
  if (random_dma_mode)
    $display("\nRandom Number Generator Seed = %d\n",rsp_random_dma.seed);
end

`endif

reg MBUS;
initial
begin
  MBUS = 0;
  if ($test$plusargs("MBUS"))
      begin
        $display("Generating vectors for at-speed test.");
        MBUS = 1;
      end
end

reg single_step;
initial
begin
  single_step = 0;
  if ($test$plusargs("single_step"))
      begin
        $display("setting single_step Mode");
        single_step = 1;
      end
end

initial
  if ($test$plusargs("dumpvars"))
      begin
        $display("Enabling dumpvars");
        $dumpvars;
      end

reg AllDiags;
initial
  begin
  AllDiags = 0;
  if ($test$plusargs("AllDiags"))
      begin
        $display("Seting All diags to run Flag");
        AllDiags = 1; 
      end
  end

reg ctrace;
initial
  begin
  ctrace = 0;
  if ($test$plusargs("ctrace"))
      begin
        $display("Seting trace compare on");
        ctrace = 1; 
      end
  end

reg eod_rst;
initial
  begin
  eod_rst = 0;
  if ($test$plusargs("eod_rst"))
      begin
        $display("Seting End of Diag Reset");
        eod_rst = 1; 
      end
  end
/********************************************************
 *
 ********************************************************/
reg [127:0] mem[0:255];
reg [127:0] temp;
integer i;

reg [31:0] fp;
initial fp = $fopen("regression.log");

/************************************************************
 * TimeOut counters 
 ***********************************************************/
reg [23:0] cycle_count;
reg [23:0] cycle_count_save;
reg TimeOut;

initial TimeOut = 0;

always @(posedge `CLK)
   if (TimeOut)
     cycle_count <= cycle_count;
   else
   if (single_step && !`tr.SingleStep)
         cycle_count <= 0;
   else
   if (!single_step && `Halt)
         cycle_count <= 0;
   else
     cycle_count <= cycle_count + 1;


always @(cycle_count)
`ifdef REALITY_RSP_REGRESSION
  if (single_step)
`else
  if (single_step || random_dma_mode)
`endif
	TimeOut = (cycle_count === `TIMEOUT_CNT_SS);
  else
	TimeOut = (cycle_count === `TIMEOUT_CNT);


always @(`Halt) cycle_count_save = (`Halt) ? cycle_count : 'h0;

/*********************************************************
 * Various initailizations
 *********************************************************/
reg dmem_dump_error;

reg [9:0] total_tests;
reg [9:0] passed_tests;
reg [9:0] failed_tests;

reg [31:0] ireg_mem[0:31];
reg [127:0] vreg_mem[0:31];

initial 
  begin
    dmem_dump_error = 0;
    total_tests  = 0;
    passed_tests = 0;
    failed_tests = 0;
  
    for (i=0; i<32;  i=i+1) ireg_mem[i] = 32'h0;
    for (i=0; i<32;  i=i+1) vreg_mem[i] = 128'h0;
    for (i=0; i<256; i=i+1) mem[i] = 128'h0;
`ifdef REALITY_RSP_REGRESSION
`else
    for (i=0; i<512; i=i+1) `IMEM[i] = 64'h0;
    for (i=0; i<256; i=i+1) begin
      			     `DMEM0[i] = 8'h0;
      			     `DMEM1[i] = 8'h0;
      			     `DMEM2[i] = 8'h0;
      			     `DMEM3[i] = 8'h0;
      			     `DMEM4[i] = 8'h0;
      			     `DMEM5[i] = 8'h0;
      			     `DMEM6[i] = 8'h0;
      			     `DMEM7[i] = 8'h0;
      			     `DMEM8[i] = 8'h0;
      			     `DMEM9[i] = 8'h0;
      			     `DMEM10[i] = 8'h0;
      			     `DMEM11[i] = 8'h0;
      			     `DMEM12[i] = 8'h0;
      			     `DMEM13[i] = 8'h0;
      			     `DMEM14[i] = 8'h0;
      			     `DMEM15[i] = 8'h0;
     			     end
`endif
  end

/**************************************************
 * Tasks Definitions
 **************************************************/
task print_imem;
input [11:0] saddr;
input [11:0] eaddr;
integer i;
begin

 saddr = saddr>>3;
 eaddr = eaddr>>3;

 if (saddr <= eaddr)
   begin
    $display("\n");
      for (i=saddr; i<=eaddr; i=i+1)
      $display("IMEM[%3h]=%8h, IMEM[%3h]=%8h", i*8, (`IMEM[i]>>32)&32'hffffffff,(i*8)+4,`IMEM[i]&32'hffffffff);
     $display("\n\n");
  end
end
endtask

task print_dmem;
input [11:0] saddr;
input [11:0] eaddr;
integer i;
begin

 saddr = saddr>>4;
 eaddr = eaddr>>4;

 if (saddr <= eaddr)
   begin
    $display("\n");

    for (i=saddr; i<=eaddr; i=i+1)
      $display("DMEM[%3h]=%16h", i*16, 
		{`DMEM15[i],`DMEM14[i],`DMEM13[i],`DMEM12[i],`DMEM11[i],`DMEM10[i],
		 `DMEM9[i], `DMEM8[i], `DMEM7[i], `DMEM6[i], `DMEM5[i], `DMEM4[i],
                 `DMEM3[i], `DMEM2[i], `DMEM1[i], `DMEM0[i]});
      $display("\n\n");
   end
end
endtask


task clean_imem;
integer i;
begin
  for (i = 0; i<512; i=i+1) `IMEM[i] = 64'h0;
end
endtask

task test_report;
begin
  $fwrite(fp,"\n\n");
  $fwrite(fp,"##########################\n");
  $fwrite(fp,"# RSP Regression Report\n");
  $fwrite(fp,"# \n");
  $fwrite(fp,"# Total Tests  :%0d\n",total_tests);
  $fwrite(fp,"#       Passed :%0d\n",passed_tests);
  $fwrite(fp,"#       Failed :%0d\n",failed_tests);
  $fwrite(fp,"##########################\n");
  $fwrite(fp,"\n");
end
endtask

`ifdef REALITY_RSP_REGRESSION

   task load_test_from_mbus;
     input [1:0] test_type;

     integer i, j;
     reg [72:0] tmp;
     reg [31:0] status;
     begin

      $display($time," START: Initializing RDRAM via MBUS.");

      if (test_type==2'b11) begin //dma test
        for (i=0; i<('h360); i= i+1) // 27K memory
           begin
	       for (j=0; j<4; j=j+1)
		  begin
	               tmp = `rdram_0.core.core[(i*4)+j];
        	       reality.r4200b_0.data[(j*2)] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
                       reality.r4200b_0.data[(j*2)+1] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};
		       `rdram_0.core.core[(i*4)+j] = ~tmp;
		  end
	       reality.r4200b_0.write_block((i*32), 2);
           end
        $display("Done Loading RDRAM");
        end

      else begin //Non DMA

        for (i=0; i<256; i= i+1)
           begin
	       for (j=0; j<4; j=j+1)
		  begin
	               tmp = `rdram_0.core.core[(i*4)+j];
        	       reality.r4200b_0.data[(j*2)] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
                       reality.r4200b_0.data[(j*2)+1] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};
		       `rdram_0.core.core[(i*4)+j] = ~tmp;
		  end
	       reality.r4200b_0.write_block((i*32), 2);
	   end
      end
      $display($time," END: Initializing RDRAM via MBUS.");

      load_test_from_rdram('hfff, 'hfff);

     end
   endtask

   task load_test_from_rdram;
     input [11:0] dmem_init_size;   // size of initialized data - 1, in bytes
     input [11:0] imem_init_size;   // size of initialized data - 1, in bytes

     integer i;
     reg [31:0] status;
     begin

	if (dmem_init_size < 7) begin 
          $display($time," START: Initializing dmem from rdram");
          reality.r4200b_0.sp_dma_read('h0   ,'h0,'h0,'h0, 7); 
					// in to dmem
        end
        else begin 
          $display($time," START: Initializing dmem from rdram");
          reality.r4200b_0.sp_dma_read('h0   ,'h0,'h0,'h0, dmem_init_size); 
					// in to dmem
        end

        status = 32'hff;
        while (status[3:2]!==0)
         begin
           repeat (200) @(posedge `CLK);
           reality.r4200b_0.read_word('h404_0010, 3);
           status = reality.r4200b_0.data[0];
         end

        $display($time," DONE: Initializing 0x%h bytes of dmem from rdram",
		dmem_init_size+1);

        $display($time," START: Initializing imem from rdram");
        reality.r4200b_0.sp_dma_read('h1000,'h1000,'h0,'h0, imem_init_size); // in to imem

        status = 32'hff;
        while (status[3:2]!==0)
         begin
           repeat (200) @(posedge `CLK);
           reality.r4200b_0.read_word('h404_0010, 3);
           status = reality.r4200b_0.data[0];
         end

        $display($time," DONE: Initializing imem from rdram");

     end
   endtask


   task dump_dmem_via_mbus;
     integer i, j;
     reg [72:0] tmp;
     reg [31:0] low_word, high_word;

     begin
       $display($time," START: Reading out DMEM via MBUS");
       for (i=0; i<512; i= i+1)
         begin
	   reality.r4200b_0.read_word(('h400_0000+(i*8)), 3);
	   low_word = reality.r4200b_0.data[0];
	   reality.r4200b_0.read_word(('h400_0000+(i*8)+4), 3);
	   high_word = reality.r4200b_0.data[0];
           tmp = `rdram_0.core.core[32'h600 + i];
           if ({low_word,high_word} != tmp)
             $display ("DMem mismatch at [%h]: Actual: %h %h , Expected: %h %h \n", 
		(i*8), low_word, high_word,tmp[63:32],tmp[31:0]);
         end
       $display("DONE: Reading DMEM via MBUS");
     end
   endtask


   task dump_dmem_top_rdram;
     input [1:0] dmem_dump_type;

     integer i;
     reg [31:0] status;
     begin
        if (dmem_dump_type == 'b00) begin		// VU type
            $display($time,"START: dumping dmem[0] in rdram");
            reality.r4200b_0.sp_dma_write('h0 ,'h2000,'h0,'h0,'h007); // to rdram ('h2000/8 = 'h400) address
        end
        else if (dmem_dump_type == 'b01) begin		// SU type
            $display($time,"START: dumping end of dmem in rdram");
            reality.r4200b_0.sp_dma_write('hf80 ,'h2000,'h0,'h0,'h07f); // to rdram ('h2000/8 = 'h400) address
        end
	else begin
            $display($time,"START: dumping dmem in rdram");		// DMA type
            reality.r4200b_0.sp_dma_write('h0   ,'h2000,'h0,'h0,'hfff); // to rdram ('h2000/8 = 'h400) address
        end

        status = 32'hff;
        while (status[3:2]!==0)
         begin
           repeat (200) @(posedge `CLK);
           reality.r4200b_0.read_word('h404_0010, 3);
           status = reality.r4200b_0.data[0];
           //$display("waitng for DMA to complete status=%h", status);
         end
	$display($time," DONE: dmem dump in rdram");
     end
   endtask

  task read_dmemINrdram_via_mbus;
     integer i,j;
     reg [71:0] tmp;
     reg [31:0] data [0:7];
    begin
        $display($time," START: reading dmem image from rdram via mbus");
         for (i=0; i<128; i=i+1)
           begin
              reality.r4200b_0.read_block('h2000 + (i*32), 2);

              tmp = `rdram_0.core.core[32'h400 + (i*4)];
	      data[0] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
	      data[1] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};

              tmp = `rdram_0.core.core[32'h400 + (i*4) + 1];
	      data[2] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
	      data[3] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};

              tmp = `rdram_0.core.core[32'h400 + (i*4) + 2];
	      data[4] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
	      data[5] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};

              tmp = `rdram_0.core.core[32'h400 + (i*4) + 3];
	      data[6] = {tmp[7:0], tmp[16:9],tmp[25:18],tmp[34:27]};
	      data[7] = {tmp[43:36], tmp[52:45],tmp[61:54],tmp[70:63]};

              for (j=0; j<8; j=j+1)
               if (reality.r4200b_0.data[j] !== data[j])

		$display("ERROR: RDRAM READ DATA MISMATCH on Address = %h", ('h2000 + (i*32) + (j*4)),
			                                    "Expected = %h", data[j], 
						            "Actual = %h", reality.r4200b_0.data[j]
			);
								
           end

        $display($time," END: reading dmem image from rdram via mbus");

    end
  endtask

   task compare_dmem_image;
     input [1:0] dmem_dump_type;

     integer i;
     integer dmem_dump_start;
     integer dump_size;
     reg [63:0] data;
     begin
      if (dmem_dump_type == 'b00) begin dump_size = 1; dmem_dump_start = 0; end
      else if (dmem_dump_type == 'b01) begin dump_size = 16; dmem_dump_start = 496; end
      else begin dump_size = 512; dmem_dump_start = 0; end
      for (i=0; i<dump_size; i=i+1)
         begin
             temp[71:0] = `rdram_0.core.core[32'h400 + i];
             data = {temp[7:0], temp[16:9],temp[25:18],temp[34:27],
                     temp[43:36], temp[52:45],temp[61:54],temp[70:63]};
	     if (data !== `rdram_0.core.core[32'h600 + i + dmem_dump_start])
		begin
		  $display("ERROR: DMEM dump in rdram missmatches with expected \n"); 
		  $display("DMEM Address(Dbl Word Alligned): %h , Actual: %h, Expected = %h \n", 
			     dmem_dump_start+i, data, `rdram_0.core.core[32'h600 + i + dmem_dump_start]); 
		  dmem_dump_error = 1;
		end
         end
     end
   endtask

`else
   task write_pc;
   input [11:0] pc;
    begin
      @(negedge `CLK);
      rspWrap.cbus_command = 3'b010;
      force `rsp_path.cbus_data = 32'h04080000; // pc address
      @(negedge `CLK);
      rspWrap.cbus_command = 3'b000;
      force `rsp_path.cbus_data = pc;    
      @(negedge `CLK);
      release `rsp_path.cbus_data;
    end
   endtask
   
   task write_status;
   input [6:0] data;
    begin
      @(posedge `CLK);
   
   // clear Status for Halt, Broke
      @(negedge `CLK);
      rspWrap.cbus_command = 3'b010;
      force `rsp_path.cbus_data = 32'h04040010; // status register address
      @(negedge `CLK);
      rspWrap.cbus_command = 3'b000;
      force `rsp_path.cbus_data = data;        
      @(negedge `CLK);
      release `rsp_path.cbus_data;
    end
   endtask

`endif

task  init_su_reg;
reg [4:0] reg_num;
reg [31:0] data;
integer i;
  begin
   for (i = 0; i<31; i=i+1) 
    begin
      reg_num = i + 1;
      data = ireg_mem[i];
      wait (`CLK === 1'b1);
      force `SRpath.w = reg_num;
      force `SRpath.bufb = data;
      force  `SRpath.wen = 1'b1;
      wait (`CLK === 1'b0);
      wait (`CLK === 1'b1);
      release `SRpath.wen;
      release `SRpath.w;
      release `SRpath.bufb;
    end
  end
endtask

task  init_vu_reg;
reg [127:0] tmp;
integer i;
  begin
      for (i = 0; i<32; i=i+1)
      begin
         tmp = vreg_mem[i];

         `VRpath.memsl0hi[i] = tmp[127:120];
         `VRpath.memsl0lo[i] = tmp[119:112];

         `VRpath.memsl1hi[i] = tmp[111:104];
         `VRpath.memsl1lo[i] = tmp[103:96];

         `VRpath.memsl2hi[i] = tmp[95:88];
         `VRpath.memsl2lo[i] = tmp[87:80];

         `VRpath.memsl3hi[i] = tmp[79:72];
         `VRpath.memsl3lo[i] = tmp[71:64];

         `VRpath.memsl4hi[i] = tmp[63:56];
         `VRpath.memsl4lo[i] = tmp[55:48];

         `VRpath.memsl5hi[i] = tmp[47:40];
         `VRpath.memsl5lo[i] = tmp[39:32];

         `VRpath.memsl6hi[i] = tmp[31:24];
         `VRpath.memsl6lo[i] = tmp[23:16];

         `VRpath.memsl7hi[i] = tmp[15:8];
         `VRpath.memsl7lo[i] = tmp[7:0];

      end
  end
endtask

task rundiag;
input [1:0] test_type;
input [255:0] test_name;
input [11:0] dmem_init_size;
input [11:0] imem_init_size;
input [1:0] dmem_dump_type;

integer i;
reg [127:0] tmp;
reg [31:0] status;
begin

dmem_dump_error = 0;


`ifdef REALITY_RSP_REGRESSION

//   for (i=0; i<1024; i= i+1) $display("core_0[%d]=%h", i, `rdram_0.core.core[i]);

   total_tests = total_tests + 1;

   if (MBUS) load_test_from_mbus(test_type);
   else	     load_test_from_rdram(dmem_init_size, imem_init_size);

   $display("clearing PC");
   reality.r4200b_0.write_word('h408_0000, 3, 32'h0); //clear pc
   $display("clearing halt,break");
   reality.r4200b_0.write_word('h404_0010, 3, (single_step<<6) | 32'h5); //clear halt,break
   if (single_step) `tr.SingleStep = 1;
  
    
   $display("Starting Test");
   @(posedge `CLK);
   `tr.di_monitor_on = 1;
   if (ctrace) `tr.test_on = 1;

   if (single_step)
    begin
     `tr.EOT = 0;
      while (!`tr.EOT)
        begin
         status = 0;
         reality.r4200b_0.read_word('h404_0010, 3);
         status = reality.r4200b_0.data[0];
	 `tr.EOT = TimeOut | `tr.trError | `tr.SingleStepError |
                  (status[1] & `tr.break_inst_seen);
	 if (!`tr.EOT & status[1])
             reality.r4200b_0.write_word('h404_0010, 3, 32'h5); //clear halt,break
        end
    end
   else
    begin
     status = 0;
     while (!status[1] && TimeOut==0 && `tr.trError==0)
       begin
        reality.r4200b_0.read_word('h404_0010, 3);
        repeat (50) @(posedge `CLK);
        status = reality.r4200b_0.data[0];
       end
    end

   if (!status[1]) // if break != 0
    begin
     $display("Setting Halt");
     reality.r4200b_0.write_word('h404_0010, 3, 32'h2); //set halt
    end

`else

   if (random_dma_mode) 
     begin
	$fwrite(rsp_random_dma.fp,"\ntime=%d,***** test %0s starts *****\n", $time, test_name); 
        `tr.eval_dmem_wr_flag(rsp_random_dma.dmem_wr_flag); 
	//$display("dmem_wr_flag = %h",rsp_random_dma.dmem_wr_flag);
     end

   if (test_type==2'b10) 
     begin
      `tr.random = 1;

      init_su_reg;
      init_vu_reg;
     end
   else
       `tr.random = 0;


   for (i = 0; i<256; i=i+1)
   begin
    temp = mem[i];
    `DMEM15[i] = temp[127:120];
    `DMEM14[i] = temp[119:112];
    `DMEM13[i] = temp[111:104];
    `DMEM12[i] = temp[103:96];
    `DMEM11[i] = temp[95:88];
    `DMEM10[i] = temp[87:80];
    `DMEM9[i]  = temp[79:72];
    `DMEM8[i]  = temp[71:64];
    `DMEM7[i]  = temp[63:56];
    `DMEM6[i]  = temp[55:48];
    `DMEM5[i]  = temp[47:40];
    `DMEM4[i]  = temp[39:32];
    `DMEM3[i]  = temp[31:24];
    `DMEM2[i]  = temp[23:16];
    `DMEM1[i]  = temp[15:8];
    `DMEM0[i]  = temp[7:0];
   end

   total_tests = total_tests + 1;

   if (single_step) 
    begin
      `tr.SingleStep = 1;
      write_status(7'h40); //Set single Step
    end
   else
      `tr.SingleStep = 0;

   @(posedge `CLK); 
   `tr.di_monitor_on = 1;
   if (ctrace) `tr.test_on = 1;

   write_pc(12'h0); //clear PC
   write_status(6'h5); //clear Broke, Halt
   wait (`Halt === 1'b0);
   wait (`Break === 1'b0);

   if (random_dma_mode) rsp_random_dma.random_dma_on = 1;

   if (single_step)
    begin
     `tr.EOT = 0;
     while (!`tr.EOT)
      begin
        wait (`Break===1'b1     | 
	       TimeOut          | 
	       `tr.trError      | 
	       `tr.RandomDone   |
	       `tr.SingleStepError 
          );
         `tr.EOT = TimeOut | `tr.trError | `tr.RandomDone | `tr.SingleStepError | 
	          (`Break==1'b1 & `tr.break_inst_seen);

	 if (!`tr.EOT) begin
	     write_status(6'h5); //clear Broke, Halt;
             wait (`Halt === 1'b0);
             wait (`Break === 1'b0);
	 end
      end
    end
   else
     wait (`Break===1'b1     | 
	    TimeOut          | 
	    `tr.trError      | 
	    `tr.RandomDone  
          ); 

   if (`Break===1'b0) 
	write_status(6'h2);
   else
      @(posedge `CLK); 

`endif

   @(posedge `CLK); 
   @(posedge `CLK); 
   @(posedge `CLK); `tr.test_on = 0; `tr.di_monitor_on = 0;

`ifdef REALITY_RSP_REGRESSION
`else
   if (random_dma_mode) 
      begin
	rsp_random_dma.random_dma_on = 0;
        @(posedge `CLK); 
	wait (rsp_random_dma.in_the_loop == 0);
        $fwrite(rsp_random_dma.fp,"\ntime=%d, ******* test %0s ends ********\n", $time, test_name); 
      end
`endif

   @(posedge `CLK); 
   @(posedge `CLK);

`ifdef REALITY_RSP_REGRESSION
   if (!test_type[1])
     begin
	dump_dmem_top_rdram(dmem_dump_type);
	compare_dmem_image(dmem_dump_type);
	if (MBUS) read_dmemINrdram_via_mbus;
     end
   //else if (test_type == 2'b11 && MBUS) 
   else if (test_type == 2'b11) 
     begin
       $display($time," START: Reading first 32 words DMEM words via MBUS");
       for (i=0; i<32; i= i+1)
         begin
           reality.r4200b_0.read_word(('h400_0000+(i*4)), 3);
	   $display("                   Word[%2d] = %h",i,reality.r4200b_0.data[0]);
         end
       $display("DONE: Reading first 32 words DMEM words via MBUS");
     end
`endif

   temp[31:0] = `r1;

        if (test_type==2'b00) $fwrite(fp,"(VU test): ");
   else if (test_type==2'b01) $fwrite(fp,"(SU test): ");
   else if (test_type==2'b10) $fwrite(fp,"(Random test): ");
   else                       $fwrite(fp,"(DMA test): ");
 
   if (TimeOut)
    begin
      $fwrite(fp,"%0s \t FAILED... \t **TIME_OUT** \t\t Time=%0d \n",test_name,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (`tr.SingleStepError)
    begin
      $fwrite(fp,"%0s \t FAILED... \t **Single Step Error** \t\t Time=%0d \n",test_name,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (`tr.trError || `tr.trError_eot)
    begin
      $fwrite(fp,"%0s \t FAILED... \t **TRACE_ERROR** \t\t Time=%0d \n",test_name,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (`Halt==0)
    begin
      $fwrite(fp,"%0s \t FAILED... \t **Halt is not SET** \t\t Time=%0d \n",test_name,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (dmem_dump_error)
    begin
      $fwrite(fp,"%0s \t FAILED... \t **DMEM dump image missmatch** \t\t Time=%0d \n",test_name,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if ( test_type==2'b00 && `r31 === 32'hdeadbeef)      //  VU tests
    begin
      $fwrite(fp,"%0s \t FAILED... \t TestNum  =  %d \t\t Time=%0d \n",test_name,`r30,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (test_type[0] && (temp & 32'hff00ffff)===32'h0) // SU tests
    begin
      $fwrite(fp,"%0s \t FAILED... \t TestNum=%d \t\t Time=%0d \n",test_name,temp[24:16],$time);
      failed_tests = failed_tests + 1;
    end
   else
   if ( test_type==2'b00 && `r31 !== 32'hfeed0000)      //  VU tests
    begin
      $fwrite(fp,"%0s \t FAILED... \t **Bizzare** \t R31=%h \tTime=%0d \n",test_name,`r31,$time);
      failed_tests = failed_tests + 1;
    end
   else
   if (test_type[0] && (temp[31:0] !== 32'hfeed0000 && temp[31:0] !== 32'hfeed) ) // SU tests
    begin
      $fwrite(fp,"%0s \t FAILED... \t **Bizzare** \t R1=%d \t Time=%0d \n",test_name,temp[15:0],$time);
      failed_tests = failed_tests + 1;
    end
   else
    begin
      $fwrite(fp,"%0s \t Passed.. \t Total_Cycles=%d \t\t Time=%0d \n", test_name,cycle_count_save,$time); 
      //$display("%0s \t Passed..  (SU_inst=%d, VU_inst=%d, Dual_Issued_inst=%d)\n",
      //		test_name,`tr.su_inst_cnt,`tr.vu_inst_cnt,`tr.di_inst_cnt); 
      passed_tests = passed_tests + 1;
    end

    TimeOut = 0;
    `tr.SingleStep = 0;

    @(posedge `CLK);
`ifdef REALITY_RSP_REGRESSION
`else
    if (eod_rst)
      begin
       rspWrap.reset_l = 0;
       @(posedge `CLK);
       @(posedge `CLK);
       @(posedge `CLK);
       rspWrap.reset_l = 1;
       @(posedge `CLK);
       @(posedge `CLK);
      end
`endif
end

endtask