README


This directory includes:
 the RAC netlist (in rac.w5.A),
 A simple test (in test1.m)
 A waves file (waves.v) and an include file.

"verilog -f inc.file" runs the test on the netlist.
The test is a very simple test that illustrates some 
of the things the user needs to know i geeting started.
Some of these things are:

1) tying up the channel signals with a pull up
2) initializing the SynClk generator
3) initializing the current control